+2004-11-06 Ulrich Weigand <uweigand@de.ibm.com>
+
+ * config/s390/2064.md ("z_o2", "z_o3"): Remove.
+ * config/s390/2084.md ("x_o2", "x_o3"): Remove.
+ ("x_fdivd"): Use also for fsqrtd type.
+ ("x_fdivs"): Use also for fsqrts type.
+ * config/s390/s390.md (attribute "type"): Remove "o2" and "o3" types.
+ ("fix_truncdfsi2_ieee"): Set type to "ftoi".
+ ("fix_truncdfsi2_ibm"): Set type to "other".
+ ("floatdidf2", "floatdisf2"): Do not clobber CC.
+ ("floatsidf2", "floatsidf2_ieee"): Likewise.
+ ("floatsisf2", "floatsisf2_ieee"): Likewise.
+ ("truncdfsf2", "truncdfsf2_ieee"): Only allow "register_operand".
+ ("truncdfsf2_ibm"): Only allow "nonimmediate_operand". Use LER
+ instead of LRER.
+ ("extendsfdf2_ibm"): Do not set atype. Set type to "floads".
+ ("sqrtdf2"): Set type to "fsqrtd".
+ ("sqrtsf2"): Set type to "fsqrts".
+
2004-11-06 Kazu Hirata <kazu@cs.umass.edu>
* tree-phinodes.c (remove_all_phi_nodes_for): Speed up using a
;; Scheduling description for z990 (cpu 2084).
-;; Copyright (C) 2003 Free Software Foundation, Inc.
+;; Copyright (C) 2003,2004 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
(eq_attr "op_type" "NN"))
"x-e1-np,x-wr-np")
-(define_insn_reservation "x_o2" 2
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "o2"))
- "x-e1-np*2,x-wr-np")
-
-(define_insn_reservation "x_o3" 3
- (and (eq_attr "cpu" "z990")
- (eq_attr "type" "o3"))
- "x-e1-np*3,x-wr-np")
-
;;
;; Floating point insns
;;
(define_insn_reservation "x_fdivd" 36
(and (eq_attr "cpu" "z990")
- (eq_attr "type" "fdivd"))
+ (eq_attr "type" "fdivd,fsqrtd"))
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_fdivs" 36
(and (eq_attr "cpu" "z990")
- (eq_attr "type" "fdivs"))
+ (eq_attr "type" "fdivs,fsqrts"))
"x_e1_t*30,x-wr-fp")
(define_insn_reservation "x_floadd" 6
floadd,floads,fstored, fstores,
fmuld,fmuls,fdivd,fdivs,
ftoi,itof,fsqrtd,fsqrts,
- other,o2,o3"
+ other"
(const_string "integer"))
;; Operand type. Used to default length attribute values
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfdbr\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "ftoi")])
(define_insn "fix_truncdfsi2_ibm"
[(set (match_operand:SI 0 "register_operand" "=d")
return "l\t%0,%N4";
}
[(set_attr "op_type" "NN")
- (set_attr "type" "ftoi")
+ (set_attr "type" "other")
(set_attr "atype" "agen")
(set_attr "length" "20")])
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:DF (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdgbr\t%0,%1"
[(set_attr "op_type" "RRE")
(define_insn "floatdisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:SF (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\t%0,%1"
[(set_attr "op_type" "RRE")
;
(define_expand "floatsidf2"
- [(parallel
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:DF 0 "register_operand" "")
+ (float:DF (match_operand:SI 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
if (TARGET_IBM_FLOAT)
(define_insn "floatsidf2_ieee"
[(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:DF (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\t%0,%1"
[(set_attr "op_type" "RRE")
;
(define_expand "floatsisf2"
- [(parallel
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC 33))])]
+ [(set (match_operand:SF 0 "register_operand" "")
+ (float:SF (match_operand:SI 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
{
if (TARGET_IBM_FLOAT)
(define_insn "floatsisf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:SI 1 "register_operand" "d")))
- (clobber (reg:CC 33))]
+ (float:SF (match_operand:SI 1 "register_operand" "d")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\t%0,%1"
[(set_attr "op_type" "RRE")
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
"TARGET_HARD_FLOAT"
"")
(define_insn "truncdfsf2_ieee"
[(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ledbr\t%0,%1"
[(set_attr "op_type" "RRE")])
(define_insn "truncdfsf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
+ (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"@
- lrer\t%0,%1
+ ler\t%0,%1
le\t%0,%1"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "floads,floads")])
sdr\t%0,%0\;ler\t%0,%1
sdr\t%0,%0\;le\t%0,%1"
[(set_attr "op_type" "NN,NN")
- (set_attr "atype" "reg,agen")
(set_attr "length" "4,6")
- (set_attr "type" "o2,o2")])
+ (set_attr "type" "floads,floads")])
;;
"@
sqdbr\t%0,%1
sqdb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsqrtd")])
;
; sqrtsf2 instruction pattern(s).
"@
sqebr\t%0,%1
sqeb\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsqrts")])
;;
;;- One complement instructions.