}
}")
-(define_insn "abssi2_power"
+(define_insn "*abssi2_power"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
"TARGET_POWER"
"abs %0,%1")
-(define_insn "abssi2_nopower"
+(define_insn_and_split "abssi2_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
+ (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
- "*
-{
- return (TARGET_POWERPC)
- ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
- : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
-}"
- [(set_attr "length" "12")])
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
- (clobber (match_scratch:SI 2 ""))]
- "! TARGET_POWER && reload_completed"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
"TARGET_POWER"
"nabs %0,%1")
-(define_insn "*nabs_no_power"
+(define_insn_and_split "*nabs_nopower"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
+ (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:SI 2 "=&r,&r"))]
"! TARGET_POWER"
- "*
-{
- return (TARGET_POWERPC)
- ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
- : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
-}"
- [(set_attr "length" "12")])
-
-(define_split
- [(set (match_operand:SI 0 "gpc_reg_operand" "")
- (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
- (clobber (match_scratch:SI 2 ""))]
- "! TARGET_POWER && reload_completed"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"fctidz %0,%1"
[(set_attr "type" "fp")])
+
+;; This only is safe if rounding mode set appropriately.
+(define_insn_and_split "floatdisf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
+ (clobber (match_scratch:DF 2 "=f"))]
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (float:DF (match_dup 1)))
+ (set (match_dup 0)
+ (float_truncate:SF (match_dup 2)))]
+ "")
\f
;; Define the DImode operations that can be done in a small number
;; of instructions. The & constraints are to prevent the register
}
}")
-(define_insn "absdi2"
+(define_insn_and_split "absdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
+ (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
- "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
- [(set_attr "length" "12")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
"")
-(define_insn "*nabsdi2"
+(define_insn_and_split "*nabsdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
+ (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
(clobber (match_scratch:DI 2 "=&r,&r"))]
"TARGET_POWERPC64"
- "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
- [(set_attr "length" "12")])
-
-(define_split
- [(set (match_operand:DI 0 "gpc_reg_operand" "")
- (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
- (clobber (match_scratch:DI 2 ""))]
- "TARGET_POWERPC64 && reload_completed"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
(define_insn_and_split "trunctfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
- (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))]
+ (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
+ (clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
- ""
+ "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_dup 1)))
(set (match_dup 0)
(float_truncate:SF (match_dup 2)))]
- "
-{
- operands[2] = gen_reg_rtx (DFmode);
-}")
+ "")
-(define_expand "floatditf2"
+(define_insn_and_split "floatditf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
+ (float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
+ (clobber (match_scratch:DF 2 "=f"))]
+ "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
+ && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2)
(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
- "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
- && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
- "{ operands[2] = gen_reg_rtx (DFmode); }")
+ "")
-(define_expand "floatsitf2"
+(define_insn_and_split "floatsitf2"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
+ (float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
+ (clobber (match_scratch:DF 2 "=f"))]
+ "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2)
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(set (match_operand:TF 0 "gpc_reg_operand" "")
(float_extend:TF (match_dup 2)))]
- "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
- "{ operands[2] = gen_reg_rtx (DFmode); }")
+ "")
-(define_expand "fix_trunctfdi2"
+(define_insn_and_split "fix_trunctfdi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+ (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
+ "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
+ && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:DI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
- "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
- && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
- "{ operands[2] = gen_reg_rtx (DFmode); }")
+ "")
-(define_expand "fix_trunctfsi2"
+(define_insn_and_split "fix_trunctfsi2"
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=f")
+ (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
+ "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
+ "#"
+ "&& reload_completed"
[(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_dup 2)))]
- "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
- "{ operands[2] = gen_reg_rtx (DFmode); }")
+ "")
(define_insn "negtf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f")