from pro_epilogue_adjust_stack_<mode>_{1,2}.
(pro_epilogue_adjust_stack_<mode>_add): Rename from
pro_epilogue_adjust_stack_<mode>_3.
* config/i386/i386.c (pro_epilogue_adjust_stack): Update for
renamed pro_epilogue_adjust_stack_{si,di}_add.
(ix86_expand_prologue): Use indirect functions. Update for renamed
pro_epilogue_adjust_stack_{si,di}_sub.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@164635
138bc75d-0d04-0410-961f-
82ee72b054a4
2010-09-26 Uros Bizjak <ubizjak@gmail.com>
+ * config/i386/i386.md (pro_epilogue_adjust_stack_<mode>_add): Merge
+ from pro_epilogue_adjust_stack_<mode>_{1,2}.
+ (pro_epilogue_adjust_stack_<mode>_add): Rename from
+ pro_epilogue_adjust_stack_<mode>_3.
+ * config/i386/i386.c (pro_epilogue_adjust_stack): Update for
+ renamed pro_epilogue_adjust_stack_{si,di}_add.
+ (ix86_expand_prologue): Use indirect functions. Update for renamed
+ pro_epilogue_adjust_stack_{si,di}_sub.
+
+2010-09-26 Uros Bizjak <ubizjak@gmail.com>
+
* config/i386/i386.md (movmsk_df): New insn.
(signbitdf): Split out of signbit<mode>2. Generate movmsk_df
sequence for TARGET_SSE_MATH.
rtx insn;
if (! TARGET_64BIT)
- insn = emit_insn (gen_pro_epilogue_adjust_stack_si_1 (dest, src, offset));
+ insn = emit_insn (gen_pro_epilogue_adjust_stack_si_add (dest,
+ src, offset));
else if (x86_64_immediate_operand (offset, DImode))
- insn = emit_insn (gen_pro_epilogue_adjust_stack_di_1 (dest, src, offset));
+ insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest,
+ src, offset));
else
{
rtx tmp;
insn = emit_insn (gen_rtx_SET (DImode, tmp, offset));
if (style < 0)
RTX_FRAME_RELATED_P (insn) = 1;
- insn = emit_insn (gen_pro_epilogue_adjust_stack_di_2 (dest, src, tmp));
+ insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp));
}
if (style >= 0)
{
rtx eax = gen_rtx_REG (Pmode, AX_REG);
rtx r10 = NULL;
+ rtx (*adjust_stack_insn)(rtx, rtx, rtx);
+
bool eax_live = false;
bool r10_live = false;
emit_insn (ix86_gen_allocate_stack_worker (eax, eax));
/* Use the fact that AX still contains ALLOCATE. */
- if (TARGET_64BIT)
- insn = gen_pro_epilogue_adjust_stack_di_3 (stack_pointer_rtx,
- stack_pointer_rtx, eax);
- else
- insn = gen_pro_epilogue_adjust_stack_si_3 (stack_pointer_rtx,
- stack_pointer_rtx, eax);
- insn = emit_insn (insn);
+ adjust_stack_insn = (TARGET_64BIT
+ ? gen_pro_epilogue_adjust_stack_di_sub
+ : gen_pro_epilogue_adjust_stack_si_sub);
+
+ insn = emit_insn (adjust_stack_insn (stack_pointer_rtx,
+ stack_pointer_rtx, eax));
if (m->fs.cfa_reg == stack_pointer_rtx)
{
;;
;; in proper program order.
-(define_insn "pro_epilogue_adjust_stack_<mode>_1"
+(define_insn "pro_epilogue_adjust_stack_<mode>_add"
[(set (match_operand:P 0 "register_operand" "=r,r")
(plus:P (match_operand:P 1 "register_operand" "0,r")
- (match_operand:P 2 "<immediate_operand>" "<i>,<i>")))
+ (match_operand:P 2 "<nonmemory_operand>" "r<i>,l<i>")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))]
""
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "pro_epilogue_adjust_stack_<mode>_2"
- [(set (match_operand:P 0 "register_operand" "=r")
- (plus:P (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "register_operand" "r")))
- (clobber (reg:CC FLAGS_REG))
- (clobber (mem:BLK (scratch)))]
- ""
- "add{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "pro_epilogue_adjust_stack_<mode>_3"
+(define_insn "pro_epilogue_adjust_stack_<mode>_sub"
[(set (match_operand:P 0 "register_operand" "=r")
(minus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 2 "register_operand" "r")))