(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_COS))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
(unspec:DF [(float_extend:DF
(match_dup 2))] UNSPEC_SINCOS_SIN))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 "=1"))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
(define_expand "atan2df3"
- [(use (match_operand:DF 0 "register_operand" "=f"))
- (use (match_operand:DF 2 "register_operand" "0"))
- (use (match_operand:DF 1 "register_operand" "u"))]
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 2 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (DFmode);
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 "=1"))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_expand "atan2sf3"
- [(use (match_operand:SF 0 "register_operand" "=f"))
- (use (match_operand:SF 2 "register_operand" "0"))
- (use (match_operand:SF 1 "register_operand" "u"))]
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 2 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (SFmode);
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 ""))])]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
(set_attr "mode" "XF")])
(define_expand "atan2xf3"
- [(use (match_operand:XF 0 "register_operand" "=f"))
- (use (match_operand:XF 2 "register_operand" "0"))
- (use (match_operand:XF 1 "register_operand" "u"))]
+ [(use (match_operand:XF 0 "register_operand" ""))
+ (use (match_operand:XF 2 "register_operand" ""))
+ (use (match_operand:XF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
(fix:SI (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 8)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 8)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
int i;
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 14)))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 14)))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx temp;
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
+ && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);