+2009-05-17 Adam Nemet <anemet@caviumnetworks.com>
+
+ * config/mips/mips.md (*zero_extend<mode>_trunchi,
+ *zero_extend<mode>_truncqi): Merge these into ...
+ (*zero_extend<GPR:mode>_trunc<SHORT:mode>): ... this new pattern.
+ Name the pattern following this as *zero_extendhi_truncqi.
+
2009-05-16 Brad Lucier <lucier@math.purdue.edu>
PR middle-end/39301
;; Combiner patterns to optimize truncate/zero_extend combinations.
-(define_insn "*zero_extend<mode>_trunchi"
+(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extend:GPR
- (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
- "TARGET_64BIT && !TARGET_MIPS16"
- "andi\t%0,%1,0xffff"
- [(set_attr "type" "logical")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*zero_extend<mode>_truncqi"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extend:GPR
- (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
+ (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
- "andi\t%0,%1,0xff"
+{
+ operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
+ return "andi\t%0,%1,%x2";
+}
[(set_attr "type" "logical")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn ""
+(define_insn "*zero_extendhi_truncqi"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI
(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]