* config/mips/mips.h (MASK_DEBUG_C, TARGET_DEBUG_C_MODE): Delete.

	(TARGET_SWITCHES): Remove -mdebugc.
	* config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
	(sltu, sleu): Remove TARGET_DEBUG_C_MODE handling.
	(seq_[sd]i, sne_[sd]i, sge_[sd]i, sle_[sd]i_reg, sgeu_[sd]i)
	(sle_[sd]i_reg): Delete.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@84095 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 655154d..c0ca7e7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2004-07-04  Richard Sandiford  <rsandifo@redhat.com>
+
+       * config/mips/mips.h (MASK_DEBUG_C, TARGET_DEBUG_C_MODE): Delete.
+       (TARGET_SWITCHES): Remove -mdebugc.
+       * config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
+       (sltu, sleu): Remove TARGET_DEBUG_C_MODE handling.
+       (seq_[sd]i, sne_[sd]i, sge_[sd]i, sle_[sd]i_reg, sgeu_[sd]i)
+       (sle_[sd]i_reg): Delete.
+
 2004-07-04  Steven Bosscher  <stevenb@suse.de>
 
        * config/iq2000/iq2000.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index ab008e4..1722041 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -176,7 +176,6 @@ extern const struct mips_cpu_info *mips_tune_info;
 
                                        /* Debug switches, not documented */
 #define MASK_DEBUG     0               /* unused */
-#define MASK_DEBUG_C   0               /* don't expand seq, etc.  */
 #define MASK_DEBUG_D   0               /* don't do define_split's */
 
                                        /* Dummy switches used only in specs */
@@ -197,7 +196,6 @@ extern const struct mips_cpu_info *mips_tune_info;
 
                                        /* Debug Modes */
 #define TARGET_DEBUG_MODE      (target_flags & MASK_DEBUG)
-#define TARGET_DEBUG_C_MODE    (target_flags & MASK_DEBUG_C)
 #define TARGET_DEBUG_D_MODE    (target_flags & MASK_DEBUG_D)
 
                                        /* Reg. Naming in .s ($21 vs. $a0) */
@@ -672,8 +670,6 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("FP exceptions are not enabled") },                            \
   {"debug",              MASK_DEBUG,                                   \
      NULL},                                                            \
-  {"debugc",             MASK_DEBUG_C,                                 \
-     NULL},                                                            \
   {"debugd",             MASK_DEBUG_D,                                 \
      NULL},                                                            \
   {"",                   (TARGET_DEFAULT                               \

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 94bd87a..6323ae3 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -6318,20 +6318,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (EQ, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 
@@ -6371,59 +6359,6 @@ dsrl\t%3,%3,1\n\
   [(set_attr "type"    "slt")
    (set_attr "mode"    "DI")])
 
-(define_insn "seq_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-       (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
-              (match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-   xor\t%0,%1,%2\;sltu\t%0,%0,1
-   xori\t%0,%1,%2\;sltu\t%0,%0,1"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (eq:SI (match_operand:SI 1 "register_operand")
-              (match_operand:SI 2 "uns_arith_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-       (xor:SI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (ltu:SI (match_dup 0)
-               (const_int 1)))]
-  "")
-
-(define_insn "seq_di"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-       (eq:DI (match_operand:DI 1 "register_operand" "%d,d")
-              (match_operand:DI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-   xor\t%0,%1,%2\;sltu\t%0,%0,1
-   xori\t%0,%1,%2\;sltu\t%0,%0,1"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (eq:DI (match_operand:DI 1 "register_operand")
-              (match_operand:DI 2 "uns_arith_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-    && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-       (xor:DI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (ltu:DI (match_dup 0)
-               (const_int 1)))]
-  "")
-
 ;; On the mips16 the default code is better than using sltu.
 
 (define_expand "sne"
@@ -6435,20 +6370,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
-    {
-      gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (NE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sne_si_zero"
@@ -6469,59 +6392,6 @@ dsrl\t%3,%3,1\n\
   [(set_attr "type"    "slt")
    (set_attr "mode"    "DI")])
 
-(define_insn "sne_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,d")
-       (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
-              (match_operand:SI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-    xor\t%0,%1,%2\;sltu\t%0,%.,%0
-    xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (ne:SI (match_operand:SI 1 "register_operand")
-              (match_operand:SI 2 "uns_arith_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-       (xor:SI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (gtu:SI (match_dup 0)
-               (const_int 0)))]
-  "")
-
-(define_insn "sne_di"
-  [(set (match_operand:DI 0 "register_operand" "=d,d")
-       (ne:DI (match_operand:DI 1 "register_operand" "%d,d")
-              (match_operand:DI 2 "uns_arith_operand" "d,K")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "@
-    xor\t%0,%1,%2\;sltu\t%0,%.,%0
-    xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (ne:DI (match_operand:DI 1 "register_operand")
-              (match_operand:DI 2 "uns_arith_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-    && !TARGET_MIPS16
-    && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
-  [(set (match_dup 0)
-       (xor:DI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (gtu:DI (match_dup 0)
-               (const_int 0)))]
-  "")
-
 (define_expand "sgt"
   [(set (match_operand:SI 0 "register_operand")
        (gt:SI (match_dup 1)
@@ -6531,20 +6401,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (GT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sgt_si"
@@ -6592,66 +6450,10 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (GE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
-(define_insn "sge_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (ge:SI (match_operand:SI 1 "register_operand" "d")
-              (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (ge:SI (match_operand:SI 1 "register_operand")
-              (match_operand:SI 2 "arith_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (lt:SI (match_dup 1)
-              (match_dup 2)))
-   (set (match_dup 0)
-       (xor:SI (match_dup 0)
-               (const_int 1)))]
-  "")
-
-(define_insn "sge_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-       (ge:DI (match_operand:DI 1 "register_operand" "d")
-              (match_operand:DI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (ge:DI (match_operand:DI 1 "register_operand")
-              (match_operand:DI 2 "arith_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (lt:DI (match_dup 1)
-              (match_dup 2)))
-   (set (match_dup 0)
-       (xor:DI (match_dup 0)
-               (const_int 1)))]
-  "")
-
 (define_expand "slt"
   [(set (match_operand:SI 0 "register_operand")
        (lt:SI (match_dup 1)
@@ -6661,17 +6463,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (LT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "slt_si"
@@ -6729,20 +6522,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (LE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sle_si_const"
@@ -6799,53 +6580,6 @@ dsrl\t%3,%3,1\n\
                                      (const_int 4)
                                      (const_int 8)))])
 
-(define_insn "sle_si_reg"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (le:SI (match_operand:SI 1 "register_operand" "d")
-              (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (le:SI (match_operand:SI 1 "register_operand")
-              (match_operand:SI 2 "register_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (lt:SI (match_dup 2)
-              (match_dup 1)))
-   (set (match_dup 0)
-       (xor:SI (match_dup 0)
-               (const_int 1)))]
-  "")
-
-(define_insn "sle_di_reg"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-       (le:DI (match_operand:DI 1 "register_operand" "d")
-              (match_operand:DI 2 "register_operand" "d")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (le:DI (match_operand:DI 1 "register_operand")
-              (match_operand:DI 2 "register_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (lt:DI (match_dup 2)
-              (match_dup 1)))
-   (set (match_dup 0)
-       (xor:DI (match_dup 0)
-               (const_int 1)))]
-  "")
-
 (define_expand "sgtu"
   [(set (match_operand:SI 0 "register_operand")
        (gtu:SI (match_dup 1)
@@ -6855,20 +6589,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (GTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sgtu_si"
@@ -6916,66 +6638,10 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (GEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
-(define_insn "sgeu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (geu:SI (match_operand:SI 1 "register_operand" "d")
-               (match_operand:SI 2 "arith_operand" "dI")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (geu:SI (match_operand:SI 1 "register_operand")
-               (match_operand:SI 2 "arith_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (ltu:SI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (xor:SI (match_dup 0)
-               (const_int 1)))]
-  "")
-
-(define_insn "sgeu_di"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-       (geu:DI (match_operand:DI 1 "register_operand" "d")
-               (match_operand:DI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (geu:DI (match_operand:DI 1 "register_operand")
-               (match_operand:DI 2 "arith_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (ltu:DI (match_dup 1)
-               (match_dup 2)))
-   (set (match_dup 0)
-       (xor:DI (match_dup 0)
-               (const_int 1)))]
-  "")
-
 (define_expand "sltu"
   [(set (match_operand:SI 0 "register_operand")
        (ltu:SI (match_dup 1)
@@ -6985,17 +6651,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (LTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sltu_si"
@@ -7053,20 +6710,8 @@ dsrl\t%3,%3,1\n\
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
 
-  /* Set up operands from compare.  */
-  operands[1] = branch_cmp[0];
-  operands[2] = branch_cmp[1];
-
-  if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
-    {
-      gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
-      DONE;
-    }
-
-  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
-    operands[2] = force_reg (SImode, operands[2]);
-
-  /* Fall through and generate default code.  */
+  gen_int_relational (LEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+  DONE;
 })
 
 (define_insn "sleu_si_const"
@@ -7122,53 +6767,6 @@ dsrl\t%3,%3,1\n\
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
                                      (const_int 4)
                                      (const_int 8)))])
-
-(define_insn "sleu_si_reg"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (leu:SI (match_operand:SI 1 "register_operand" "d")
-               (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "SI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand")
-       (leu:SI (match_operand:SI 1 "register_operand")
-               (match_operand:SI 2 "register_operand")))]
-  "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (ltu:SI (match_dup 2)
-               (match_dup 1)))
-   (set (match_dup 0)
-       (xor:SI (match_dup 0)
-               (const_int 1)))]
-  "")
-
-(define_insn "sleu_di_reg"
-  [(set (match_operand:DI 0 "register_operand" "=d")
-       (leu:DI (match_operand:DI 1 "register_operand" "d")
-               (match_operand:DI 2 "register_operand" "d")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
-  [(set_attr "type"    "multi")
-   (set_attr "mode"    "DI")
-   (set_attr "length"  "8")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand")
-       (leu:DI (match_operand:DI 1 "register_operand")
-               (match_operand:DI 2 "register_operand")))]
-  "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
-   && !TARGET_MIPS16"
-  [(set (match_dup 0)
-       (ltu:DI (match_dup 2)
-               (match_dup 1)))
-   (set (match_dup 0)
-       (xor:DI (match_dup 0)
-               (const_int 1)))]
-  "")
 \f
 ;;
 ;;  ....................