* config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,

	REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
	(CONSTRAINT_LEN): Add entry for 'q'.
	(REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
	Add 'q' constraints.
	(REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
	(CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.

	* config/bfin/bfin.md (add_with_carry): New pattern.
	(s_or_u, su_optab, su_modifier): New code macros/attrs.
	(<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
	<su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
	support unsigned multiplies too.  Removed incorrect commutativity from
	operand 1 constraint where appropriate.
	(usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
	patterns.
	(<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
	<su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
	New patterns.
	(usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
	usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
	usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
	usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
	usmulhisi_hh_huh): New patterns.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@122373 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 51c99a6..f6b8edb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -15,6 +15,31 @@
        (bfin_reorder_loops): New function.
        (bfin_reorg_loops): Use these three new functions.
 
+       * config/bfin/bfin.h (enum reg_class, REG_CLASS_NAMES,
+       REG_CLASS_CONTENTS): Add D0REGS through D7REGS.
+       (CONSTRAINT_LEN): Add entry for 'q'.
+       (REG_CLASS_FROM_CONSTRAINT): Renamed from REG_CLASS_FROM_LETTER.
+       Add 'q' constraints.
+       (REGNO_REG_CLASS): For R0 through R7, return corresponding regclass.
+       (CLASS_LIKELY_SPILLED_P): True for R0, R1 and R2.
+
+       * config/bfin/bfin.md (add_with_carry): New pattern.
+       (s_or_u, su_optab, su_modifier): New code macros/attrs.
+       (<su_optab>hisi_ll, <su_optab>hisi_lh, <su_optab>hisi_hl,
+       <su_optab>hisi_hh): Renamed from mulhisi_xx patterns; macroized to
+       support unsigned multiplies too.  Removed incorrect commutativity from
+       operand 1 constraint where appropriate.
+       (usmulhisi_ull, usmulhisi_ulh, usmulhisi_uhl, usmulhisi_uhh): New
+       patterns.
+       (<su_optab>hisi_ll_lh, <su_optab>hisi_ll_hl, <su_optab>hisi_ll_hh,
+       <su_optab>hisi_lh_hl, <su_optab>hisi_lh_hh, <su_optab>hisi_hl_hh):
+       New patterns.
+       (usmulhisi_ll_lul, usmulhisi_ll_luh, usmulhisi_ll_hul,
+       usmulhisi_ll_huh, usmulhisi_lh_lul, usmulhisi_lh_luh, usmulhisi_lh_hul,
+       usmulhisi_lh_huh, usmulhisi_hl_lul, usmulhisi_hl_luh, usmulhisi_hl_hul,
+       usmulhisi_hl_huh, usmulhisi_hh_lul, usmulhisi_hh_luh, usmulhisi_hh_hul,
+       usmulhisi_hh_huh): New patterns.
+
 2007-02-27  Andreas Schwab  <schwab@suse.de>
 
        * Makefile.in (TEXI_GCCINSTALL_FILES): Add gcc-common.texi.

diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index 9b9b78a..3085a38 100644 (file)
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -411,6 +411,14 @@ enum reg_class
   CCREGS,
   EVEN_DREGS,
   ODD_DREGS,
+  D0REGS,
+  D1REGS,
+  D2REGS,
+  D3REGS,
+  D4REGS,
+  D5REGS,
+  D6REGS,
+  D7REGS,
   DREGS,
   FDPIC_REGS,
   FDPIC_FPTR_REGS,
@@ -447,6 +455,14 @@ enum reg_class
    "CCREGS",           \
    "EVEN_DREGS",       \
    "ODD_DREGS",                \
+   "D0REGS",           \
+   "D1REGS",           \
+   "D2REGS",           \
+   "D3REGS",           \
+   "D4REGS",           \
+   "D5REGS",           \
+   "D6REGS",           \
+   "D7REGS",           \
    "DREGS",            \
    "FDPIC_REGS",       \
    "FDPIC_FPTR_REGS",  \
@@ -491,6 +507,14 @@ enum reg_class
     { 0x00000000,    0x4 },            /* CCREGS */  \
     { 0x00000055,    0 },              /* EVEN_DREGS */   \
     { 0x000000aa,    0 },              /* ODD_DREGS */   \
+    { 0x00000001,    0 },              /* D0REGS */   \
+    { 0x00000002,    0 },              /* D1REGS */   \
+    { 0x00000004,    0 },              /* D2REGS */   \
+    { 0x00000008,    0 },              /* D3REGS */   \
+    { 0x00000010,    0 },              /* D4REGS */   \
+    { 0x00000020,    0 },              /* D5REGS */   \
+    { 0x00000040,    0 },              /* D6REGS */   \
+    { 0x00000080,    0 },              /* D7REGS */   \
     { 0x000000ff,    0 },              /* DREGS */   \
     { 0x00000800,    0x000 },          /* FDPIC_REGS */   \
     { 0x00000200,    0x000 },          /* FDPIC_FPTR_REGS */   \
@@ -537,7 +561,7 @@ enum reg_class
 
 /* Get reg_class from a letter such as appears in the machine description.  */
 
-#define REG_CLASS_FROM_LETTER(LETTER)  \
+#define REG_CLASS_FROM_CONSTRAINT(LETTER, STR) \
   ((LETTER) == 'a' ? PREGS :            \
    (LETTER) == 'Z' ? FDPIC_REGS :      \
    (LETTER) == 'Y' ? FDPIC_FPTR_REGS : \
@@ -559,6 +583,16 @@ enum reg_class
    (LETTER) == 'x' ? MOST_REGS :       \
    (LETTER) == 'y' ? PROLOGUE_REGS :   \
    (LETTER) == 'w' ? NON_A_CC_REGS :   \
+   (LETTER) == 'q' \
+    ? ((STR)[1] == '0' ? D0REGS \
+       : (STR)[1] == '1' ? D1REGS \
+       : (STR)[1] == '2' ? D2REGS \
+       : (STR)[1] == '3' ? D3REGS \
+       : (STR)[1] == '4' ? D4REGS \
+       : (STR)[1] == '5' ? D5REGS \
+       : (STR)[1] == '6' ? D6REGS \
+       : (STR)[1] == '7' ? D7REGS \
+       : NO_REGS) : \
    NO_REGS)
 
 /* The same information, inverted:
@@ -567,7 +601,14 @@ enum reg_class
    or could index an array.  */
 
 #define REGNO_REG_CLASS(REGNO) \
- ((REGNO) < REG_P0 ? DREGS                             \
+((REGNO) == REG_R0 ? D0REGS                            \
+ : (REGNO) == REG_R1 ? D1REGS                          \
+ : (REGNO) == REG_R2 ? D2REGS                          \
+ : (REGNO) == REG_R3 ? D3REGS                          \
+ : (REGNO) == REG_R4 ? D4REGS                          \
+ : (REGNO) == REG_R5 ? D5REGS                          \
+ : (REGNO) == REG_R6 ? D6REGS                          \
+ : (REGNO) == REG_R7 ? D7REGS                          \
  : (REGNO) < REG_I0 ? PREGS                            \
  : (REGNO) == REG_ARGP ? PREGS                         \
  : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS      \
@@ -590,6 +631,9 @@ enum reg_class
 #define CLASS_LIKELY_SPILLED_P(CLASS) \
     ((CLASS) == PREGS_CLOBBERED \
      || (CLASS) == PROLOGUE_REGS \
+     || (CLASS) == D0REGS \
+     || (CLASS) == D1REGS \
+     || (CLASS) == D2REGS \
      || (CLASS) == CCREGS)
 
 /* Do not allow to store a value in REG_CC for any mode */
@@ -1030,7 +1074,7 @@ do {                                             \
 #define CONST_3UBIT_IMM_P(VALUE) ((VALUE) >= 0 && (VALUE) <= 7)
 
 #define CONSTRAINT_LEN(C, STR)                 \
-    ((C) == 'P' || (C) == 'M' || (C) == 'N' ? 2        \
+    ((C) == 'P' || (C) == 'M' || (C) == 'N' || (C) == 'q' ? 2  \
      : (C) == 'K' ? 3                          \
      : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
 

diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 6e609e8..7bdde27 100644 (file)
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -1007,6 +1007,24 @@
 
 ;; DImode arithmetic operations
 
+(define_insn "add_with_carry"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+                 (match_operand:SI 2 "nonmemory_operand" "Ks7,d")))
+   (set (match_operand:SI 3 "register_operand" "=d,d")
+       (truncate:SI
+        (lshiftrt:DI (plus:DI (zero_extend:DI (match_dup 1))
+                              (zero_extend:DI (match_dup 2)))
+                     (const_int 32))))
+   (clobber (reg:CC 34))]
+  ""
+  "@
+   %0 += %2; cc = ac0; %3 = cc;
+   %0 = %0 + %2; cc = ac0; %3 = cc;"
+  [(set_attr "type" "alu0")
+   (set_attr "length" "6")
+   (set_attr "seq_insns" "multi")])
+
 (define_insn "adddi3"
   [(set (match_operand:DI 0 "register_operand" "=&d,&d,&d")
         (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
@@ -3249,54 +3267,491 @@
 }
   [(set_attr "type" "dsp32")])
 
-(define_insn "mulhisi_ll"
+(define_code_macro s_or_u [sign_extend zero_extend])
+(define_code_attr su_optab [(sign_extend "mul")
+                           (zero_extend "umul")])
+(define_code_attr su_modifier [(sign_extend "IS")
+                              (zero_extend "FU")])
+
+(define_insn "<su_optab>hisi_ll"
   [(set (match_operand:SI 0 "register_operand" "=d")
-       (mult:SI (sign_extend:SI
+       (mult:SI (s_or_u:SI
                  (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
                                 (parallel [(const_int 0)])))
-                (sign_extend:SI
+                (s_or_u:SI
                  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
                                 (parallel [(const_int 0)])))))]
   ""
-  "%0 = %h1 * %h2 (IS)%!"
+  "%0 = %h1 * %h2 (<su_modifier>)%!"
   [(set_attr "type" "dsp32")])
 
-(define_insn "mulhisi_lh"
+(define_insn "<su_optab>hisi_lh"
   [(set (match_operand:SI 0 "register_operand" "=d")
-       (mult:SI (sign_extend:SI
-                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
                                 (parallel [(const_int 0)])))
-                (sign_extend:SI
+                (s_or_u:SI
                  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
                                 (parallel [(const_int 1)])))))]
   ""
-  "%0 = %h1 * %d2 (IS)%!"
+  "%0 = %h1 * %d2 (<su_modifier>)%!"
   [(set_attr "type" "dsp32")])
 
-(define_insn "mulhisi_hl"
+(define_insn "<su_optab>hisi_hl"
   [(set (match_operand:SI 0 "register_operand" "=d")
-       (mult:SI (sign_extend:SI
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+                                (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+                                (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %d1 * %h2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_hh"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+       (mult:SI (s_or_u:SI
                  (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
                                 (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+                                (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %d2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+;; Additional variants for signed * unsigned multiply.
+
+(define_insn "usmulhisi_ull"
+  [(set (match_operand:SI 0 "register_operand" "=W")
+       (mult:SI (zero_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
+                                (parallel [(const_int 0)])))
                 (sign_extend:SI
                  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
                                 (parallel [(const_int 0)])))))]
   ""
-  "%0 = %d1 * %h2 (IS)%!"
+  "%0 = %h2 * %h1 (IS,M)%!"
   [(set_attr "type" "dsp32")])
 
-(define_insn "mulhisi_hh"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-       (mult:SI (sign_extend:SI
+(define_insn "usmulhisi_ulh"
+  [(set (match_operand:SI 0 "register_operand" "=W")
+       (mult:SI (zero_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+                                (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d2 * %h1 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_uhl"
+  [(set (match_operand:SI 0 "register_operand" "=W")
+       (mult:SI (zero_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+                                (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h2 * %d1 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_uhh"
+  [(set (match_operand:SI 0 "register_operand" "=W")
+       (mult:SI (zero_extend:SI
                  (vec_select:HI (match_operand:V2HI 1 "register_operand" "%d")
                                 (parallel [(const_int 1)])))
                 (sign_extend:SI
                  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
                                 (parallel [(const_int 1)])))))]
   ""
-  "%0 = %d1 * %d2 (IS)%!"
+  "%0 = %d2 * %d1 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+;; Parallel versions of these operations.  First, normal signed or unsigned
+;; multiplies.
+
+(define_insn "<su_optab>hisi_ll_lh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %h1 * %d2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_ll_hl"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %d1 * %h2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_ll_hh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_lh_hl"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %d1 * %h2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_lh_hh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %d1 * %d2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "<su_optab>hisi_hl_hh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (s_or_u:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (s_or_u:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %h2, %3 = %d1 * %d2 (<su_modifier>)%!"
+  [(set_attr "type" "dsp32")])
+
+;; Special signed * unsigned variants.
+
+(define_insn "usmulhisi_ll_lul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_ll_luh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_ll_hul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_ll_huh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_lh_lul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_lh_luh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_lh_hul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_lh_huh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %h1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hl_lul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %d1 * %h2, %3 = %h1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hl_luh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %h2, %3 = %h1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hl_hul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %d1 * %h2, %3 = %d1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hl_huh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 0)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %h2, %3 = %d1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hh_lul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %d1 * %d2, %3 = %h1 * %h2 (IS,M)%!"
   [(set_attr "type" "dsp32")])
 
+(define_insn "usmulhisi_hh_luh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %d2, %3 = %h1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hh_hul"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))))]
+  ""
+  "%0 = %d1 * %d2, %3 = %d1 * %h2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "usmulhisi_hh_huh"
+  [(set (match_operand:SI 0 "register_operand" "=q0,q2,q4,q6")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 1 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))
+                (sign_extend:SI
+                 (vec_select:HI (match_operand:V2HI 2 "register_operand" "d,d,d,d")
+                                (parallel [(const_int 1)])))))
+   (set (match_operand:SI 3 "register_operand" "=q1,q3,q5,q7")
+       (mult:SI (sign_extend:SI
+                 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+                (zero_extend:SI
+                 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
+  "%0 = %d1 * %d2, %3 = %d1 * %d2 (IS,M)%!"
+  [(set_attr "type" "dsp32")])
+
+;; Vector neg/abs.
+
 (define_insn "ssnegv2hi2"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
        (ss_neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]