/* These variables are used for communication between the following functions.
They indicate various things about the current function being compiled
that are used to tell what kind of prologue, epilogue and procedure
- descriptior to generate. */
+ descriptor to generate. */
/* Nonzero if we need a stack procedure. */
enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
int nop_count = (align - ofs) / 4;
rtx where;
- /* Insert nops before labels, branches, and calls to truely merge
+ /* Insert nops before labels, branches, and calls to truly merge
the execution of the nops with the previous instruction group. */
where = prev_nonnote_insn (i);
if (where)
{
/* There's some dispute as to whether this should be 1 or 2. However,
experiments seem to show that in pathological cases a setting of
- 1 degrades less severly than a setting of 2. This could change if
+ 1 degrades less severely than a setting of 2. This could change if
other parts of the compiler change their behavior. */
arm_constant_limit = 1;
triggers a bug on most SA-110 based devices, such that the stack
pointer won't be correctly restored if the instruction takes a
- page fault. We work around this problem by poping r3 along with
+ page fault. We work around this problem by popping r3 along with
the other registers, since that is never slower than executing
another instruction.
(set_attr "type" "mult")]
)
-;; Unnamed template to match long long multiply-accumlate (smlal)
+;; Unnamed template to match long long multiply-accumulate (smlal)
(define_insn "*mulsidi3adddi"
[(set (match_operand:DI 0 "s_register_operand" "=&r")
(set_attr "predicable" "yes")]
)
-;; Unnamed template to match long long unsigned multiply-accumlate (umlal)
+;; Unnamed template to match long long unsigned multiply-accumulate (umlal)
(define_insn "*umulsidi3adddi"
[(set (match_operand:DI 0 "s_register_operand" "=&r")
dont_pop_ar3 = 0; /* If we use ar3, we need to pop it. */
if (size || current_function_args_size)
{
- /* If we are ommitting the frame pointer, we still have
+ /* If we are omitting the frame pointer, we still have
to make space for it so the offsets are correct
unless we don't use anything on the stack at all. */
size += 1;
; a register satisying the 'f' constraint is used as a dst operand,
; the CC gets clobbered (except for LDFcond).
-; The ! in front of the 'b' constaint says to GCC to disparage the
+; The ! in front of the 'b' constraint says to GCC to disparage the
; use of this constraint. The 'b' constraint applies only to the SP.
; Note that we deal with the condition code CC like some of the RISC
; delayed branch slots.
; Since the C[34]x has many instructions that set the CC, we pay the
-; price of having to explicity define which insns clobber the CC
+; price of having to explicitly define which insns clobber the CC
; (rather than using the macro NOTICE_UPDATE_CC).
; Note that many patterns say that the CC is clobbered when in fact
;
; MULF
;
-; The C3x MPYF only uses 24 bit precision while the C4x uses 32 bit precison.
+; The C3x MPYF only uses 24-bit precision while the C4x uses 32-bit precision.
;
(define_expand "mulhf3"
[(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
"stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
-; The following two peepholes remove an unecessary load
+; The following two peepholes remove an unnecessary load
; often found at the end of a function. These peepholes
; could be generalized to other binary operators. They shouldn't
; be required if we run a post reload mop-up pass.
/* This needs to be at least 32 bits. */
extern int target_flags;
-/* Currently this just affects aligment. FIXME: Redundant with
+/* Currently this just affects alignment. FIXME: Redundant with
TARGET_ALIGN_BY_32, or put machine stuff here? */
#define TARGET_MASK_SVINTO 1
#define TARGET_SVINTO (target_flags & TARGET_MASK_SVINTO)
/* If we would ever need an exact mapping between canonical register
number and dwarf frame register, we would either need to include all
- registers in the gcc decription (with some marked fixed of course), or
+ registers in the gcc description (with some marked fixed of course), or
an inverse mapping from dwarf register to gcc register. There is one
need in dwarf2out.c:expand_builtin_init_dwarf_reg_sizes. Right now, I
don't see that we need exact correspondence between DWARF *frame*
;; There are several instructions that are orthogonal in size, and seems
;; they could be matched by a single pattern without a specified size
;; for the operand that is orthogonal. However, this did not work on
-;; gcc-2.7.2 (and problably not on gcc-2.8.1), relating to that when a
+;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
;; constant is substituted into an operand, the actual mode must be
;; deduced from the pattern. There is reasonable hope that that has been
;; fixed, so FIXME: try again.
;; The possible values are "yes", "no" and "has_slot". Yes/no means if
;; the insn is slottable or not. Has_slot means that the insn is a
;; return insn or branch insn (which are not considered slottable since
-;; that is generally true). Having the semmingly illogical value
+;; that is generally true). Having the seemingly illogical value
;; "has_slot" means we do not have to add another attribute just to say
;; that an insn has a delay-slot, since it also infers that it is not
;; slottable. Better names for the attribute were found to be longer and
"movs.b %1,%0"
[(set_attr "slottable" "yes,yes,no")])
-;; To do a byte->word exension, extend to dword, exept that the top half
+;; To do a byte->word extension, extend to dword, exept that the top half
;; of the register will be clobbered. FIXME: Perhaps this is not needed.
(define_insn "extendqihi2"
unsigned int frame_size; /* # Bytes in current frame. */
unsigned int gmask; /* Mask of saved registers. */
unsigned int save_fp; /* Nonzero if frame pointer must be saved. */
- unsigned int save_rp; /* Nonzero if return popinter must be saved. */
+ unsigned int save_rp; /* Nonzero if return pointer must be saved. */
int initialised; /* Nonzero if frame size already calculated. */
};
/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
Returns the number of argument registers required to hold *part* of
a parameter of machine mode MODE and tree type TYPE (which may be
- NULL if the type is not known). If the argument fits entirly in
+ NULL if the type is not known). If the argument fits entirely in
the argument registers, or entirely on the stack, then 0 is returned.
CUM is the number of argument registers already used by earlier
parameters to the function. */
/* Output a double word move.
It must be REG<-REG, REG<-MEM, MEM<-REG or REG<-CONST.
- On the FR30 we are contrained by the fact that it does not
+ On the FR30 we are constrained by the fact that it does not
support offsetable addresses, and so we have to load the
address of the secnd word into the second destination register
before we can use it. */
jmp @r0
The no-ops are to guarantee that the static chain and final
- target are 32 bit ailgned within the trampoline. That allows us to
+ target are 32 bit aligned within the trampoline. That allows us to
initialize those locations with simple SImode stores. The alternative
would be to use HImode stores. */
;; We need some trickery to be able to handle the addition of
;; large (ie outside +/- 16) constants. We need to be able to
;; handle this because reload assumes that it can generate add
-;; instructions with arbitary sized constants.
+;; instructions with arbitrary sized constants.
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
nested compares can be done. The csubcc and caddcc instructions don't
have enough bits to specify both a CC register to be set and a CR register
to do the test on, so the same bit number is used for both. Needless to
- say, this is rather inconvient for GCC. */
+ say, this is rather inconvenient for GCC. */
rtx nested_cc_reg;
/* Extra CR registers used for &&, ||. */
\f
/* Under frv, all of the work is done via frv_expand_epilogue, but
- this function provides a convient place to do cleanup. */
+ this function provides a convenient place to do cleanup. */
static void
frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
/* Set frv_insn_packing_flag to FALSE if the next instruction should
be packed with this one. Set it to TRUE otherwise. If the next
- instruction is an asm insntruction, this statement will set the
+ instruction is an asm instruction, this statement will set the
flag to TRUE, and that value will still hold when the asm operands
themselves are printed. */
frv_insn_packing_flag = ! (insn && INSN_P (insn)
}
/* Return 1 if operand is a symbolic reference when a PIC option is specified
- that takes 3 seperate instructions to form. */
+ that takes 3 separate instructions to form. */
int
pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
\f
/* Split a SCC instruction into component parts, returning a SEQUENCE to hold
- the seperate insns. */
+ the separate insns. */
rtx
frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
}
\f
-/* Split a conditonal move into constituent parts, returning a SEQUENCE
+/* Split a conditional move into constituent parts, returning a SEQUENCE
containing all of the insns. */
rtx
}
/* Clear the VLIW start flag on random USE and CLOBBER insns, which is
- set on the USE insn that preceeds the return, and potentially on
+ set on the USE insn that precedes the return, and potentially on
CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
holding the case table labels. */
pattern_code = GET_CODE (PATTERN (insn));
}
/* Given that ARG is being passed as operand OPNUM to instruction ICODE,
- check whether ARG satisfies the operand's contraints. If it doesn't,
+ check whether ARG satisfies the operand's constraints. If it doesn't,
copy ARG to a temporary register and return that. Otherwise return ARG
itself. */
first regular expression *and* the reservation described by
the second regular expression *and* etc.
- 4. "*" is used for convinience and simply means sequence in
+ 4. "*" is used for convenience and simply means sequence in
which the regular expression are repeated NUMBER times with
cycle advancing (see ",").
;; Note - it is the backend's responsibility to fill any unfilled delay slots
;; at assembler generation time. This is usually done by adding a special print
-;; operand to the delayed insrtuction, and then in the PRINT_OPERAND function
+;; operand to the delayed instruction, and then in the PRINT_OPERAND function
;; calling dbr_sequence_length() to determine how many delay slots were filled.
;; For example:
;;
;; Note - it is best to only have one movsi pattern and to handle
;; all the various contingencies by the use of alternatives. This
-;; allows reload the greatest amount of flexability (since reload will
+;; allows reload the greatest amount of flexibility (since reload will
;; only choose amoungst alternatives for a selected insn, it will not
;; replace the insn with another one).
;; constants into memory when the destination is a floating-point register.
;; That may make a function use a PIC pointer when it didn't before, and we
;; cannot change PIC usage (and hence stack layout) so late in the game.
-;; The resulting sequences for loading cosntants into FPRs are preferable
+;; The resulting sequences for loading constants into FPRs are preferable
;; even when we're not generating PIC code.
(define_insn "*movsi_load"
;; "anddi3 %0,%1,%2"
;; [(set_attr "length" "4")])
-;; Includive OR, 64 bit integers
+;; Inclusive OR, 64 bit integers
;; (define_insn "iordi3"
;; [(set (match_operand:DI 0 "register_operand" "=r")
;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
[(set_attr "length" "4")
(set_attr "type" "mqsath")])
-;; Set hi/lo instrctions: type "mset"
+;; Set hi/lo instructions: type "mset"
(define_insn "mhsetlos"
[(set (match_operand:SI 0 "fpr_operand" "=f")
extern func_ptr __EH_FRAME_BEGIN__[];
-/* Register the exeception handling table as the first constructor */
+/* Register the exception handling table as the first constructor */
void
__frv_register_eh (void)
{
/* Note, do not declare __{,de}register_frame_info weak as it seems
to interfere with the pic support. */
-/* Unregister the exeception handling table as a deconstructor */
+/* Unregister the exception handling table as a deconstructor */
void
__frv_deregister_eh (void)
{
(and (eq_attr "type" "idiv")
(eq_attr "memory" "load,both")))
"athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))")
-;; The paralelism of string instructions is not documented. Model it same way
+;; The parallelism of string instructions is not documented. Model it same way
;; as idiv to create smaller automata. This probably does not matter much.
(define_insn_reservation "athlon_str" 6
(and (eq_attr "cpu" "athlon,k8")
(and (eq_attr "cpu" "k8")
(eq_attr "type" "ssemul"))
"athlon-double,athlon-fpsched,(athlon-fmul*2)")
-;; divsd timmings. divss is faster
+;; divsd timings. divss is faster
(define_insn_reservation "athlon_ssediv_load" 20
(and (eq_attr "cpu" "athlon")
(and (eq_attr "type" "ssediv")
\f
/* Return the regparm value for a fuctio with the indicated TYPE and DECL.
DECL may be NULL when calling function indirectly
- or considerling a libcall. */
+ or considering a libcall. */
static int
ix86_function_regparm (tree type, tree decl)
}
}
-/* Expand prologue or epilogue stack adjustement.
+/* Expand prologue or epilogue stack adjustment.
The pattern exist to put a dependency on all ebp-based memory accesses.
STYLE should be negative if instructions should be marked as frame related,
zero if %r11 register is live and cannot be freely used and positive
return "push{l}\t%1";
default:
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
}
return "push{q}\t%q1";
default:
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
}
(match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
"!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
{
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
(match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
"TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
{
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
"optimize_size"
{
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
"!optimize_size"
{
- /* This insn should be already splitted before reg-stack. */
+ /* This insn should be already split before reg-stack. */
abort ();
}
[(set_attr "type" "multi")
assume that /usr/gnu is the prefix for the GNU tools, because thats
where the SCO provided ones go. This is especially important for
include and library search path ordering. We want to look in /usr/gnu
- first, becuase frequently people are linking against -lintl, and they
+ first because frequently people are linking against -lintl, and they
MEAN to link with gettext. What they get is the SCO intl library. Its
a REAL pity that GNU gettext chose that name; perhaps in a future
version they can be persuaded to change it to -lgnuintl and have a
;; ::
;; ::::::::::::::::::::
-;; ??? Emiting a NOP instruction isn't very useful. This should probably
+;; ??? Emitting a NOP instruction isn't very useful. This should probably
;; be emitting ";;" to force a break in the instruction packing.
;; No operation, needed in case the user uses -g but not -O.
OUT_AS2 (mov, w, %L0);
OUT_AS2 (add, spl, w);
epilogue_size += 4;
- /* fall-thru */
+ /* fall-through */
case 0:
break;
case 1:
OUT_AS2 (mov, w, %H0);
OUT_AS2 (add, sph, w);
epilogue_size += 4;
- /* fall-thru */
+ /* fall-through */
case 0:
break;
case 0x100:
OUT_AS2 (mov, w, %L0);
OUT_AS2 (add, spl, w);
epilogue_size += 4;
- /* fall-thru */
+ /* fall-through */
case 0:
break;
OUT_AS2 (mov, w, %H0);
OUT_AS2 (add, sph, w);
epilogue_size += 4;
- /* fall-thru */
+ /* fall-through */
case 0:
break;
if (REGNO (x) == REG_IP)
return (GET_MODE_SIZE (mode) == 1) ? 'R' : 0;
- /* We can indirect thru DP or SP register. */
+ /* We can indirect through DP or SP register. */
if (strict ? REG_OK_FOR_BASE_STRICT_P (x)
: REG_OK_FOR_BASE_NOSTRICT_P (x))
return 'S';
op2 = tmp;
}
- /* Don't let anything but R+I thru.. */
+ /* Don't let anything but R+I through.. */
if (! REG_P (op1)
|| REG_P (op2)
|| GET_CODE (op2) != CONST_INT)
{
case SUBREG:
addr = alter_subreg (&addr);
- /* fall-thru */
+ /* fall-through */
case REG:
fprintf (file, "(%s)",
{
case SUBREG:
x = alter_subreg (&x);
- /* fall-thru */
+ /* fall-through */
case REG:
fprintf (file, reg_names[true_regnum (x) + abcd]);
case GTU:
code = NE; /* Anything nonzero is GTU. */
- /* fall-thru */
+ /* fall-through */
case EQ:
case NE: /* Test all the bits, result in
case GTU:
if (imm_sub)
{
- /* > 0xffff never suceeds! */
+ /* > 0xffff never succeeds! */
if ((INTVAL (operands[1]) & 0xffff) != 0xffff)
{
operands[3] = GEN_INT (INTVAL (operands[1]) + 1);
{
if ((INTVAL (operands[1]) & 0xffff) == 0xffff)
{
- /* <= 0xffff always suceeds. */
+ /* <= 0xffff always succeeds. */
OUT_AS1 (page, %2);
OUT_AS1 (jmp, %2);
}
case GTU:
if (imm_sub)
{
- /* > 0xffffffff never suceeds! */
+ /* > 0xffffffff never succeeds! */
if ((unsigned HOST_WIDE_INT)(INTVAL (operands[1]) & 0xffffffff)
!= 0xffffffff)
{
if ((unsigned HOST_WIDE_INT)(INTVAL (operands[1]) & 0xffffffff)
== 0xffffffff)
{
- /* <= 0xffffffff always suceeds. */
+ /* <= 0xffffffff always succeeds. */
OUT_AS1 (page, %2);
OUT_AS1 (jmp, %2);
}
/* As part of the machine-dependent reorg we scan loads and reloads of
DP to see where any are redundant. This does happens because we
are able to subsequently transform things in interesting ways. Sometimes
- gcc also does unecessary reloads too so we try to eliminate these too. */
+ gcc also does unnecessary reloads too so we try to eliminate these too. */
static void
mdr_try_dp_reload_elim (first_insn)
}
/* When we're looking to see if we've finished we count the number of
- paths throught the code labels where we weren't able to definitively
+ paths through the code labels where we weren't able to definitively
track DP.
This number is used to see if we're converging on a solution.
If this hits zero then we've fully converged, but if this stays the
}
/* When we're looking to see if we've finished we count the number of
- paths throught the code labels where we weren't able to definitively
+ paths through the code labels where we weren't able to definitively
track WREG. This number is used to see if we're converging on a
solution.
If this hits zero then we've fully converged, but if this stays the
x = XEXP (x, 0);
- /* fall thru */
+ /* fall through */
case REG:
if (IS_PSEUDO_P (x))
;; d - non-pointer registers (not SP, DP, IP)
;; u - non-SP registers (everything except SP)
;;
-;; R - Indirect thru IP - Avoid this except for QI mode, since we
+;; R - Indirect through IP - Avoid this except for QI mode, since we
;; can't access extra bytes.
;; S - Short (stack/dp address). Pointer with 0..127 displacement
;; Note that 0(SP) has undefined contents due to post-decrement push
macro is used in only one place: `find_reloads_address' in reload.c.
For M68HC11, we handle large displacements of a base register
- by splitting the addend accors an addhi3 insn.
+ by splitting the addend across an addhi3 insn.
For M68HC12, the 64K offset range is available.
*/
#define MASK_RTD (1<<16)
#define TARGET_RTD (target_flags & MASK_RTD)
-/* Support A5 relative data seperate from text.
+/* Support A5 relative data separate from text.
* This option implies -fPIC, however it inhibits the generation of the
* A5 save/restore in functions and the loading of a5 with a got pointer.
*/
/* Set up the frame pointer, if we're using one. In mips16 code,
we point the frame pointer ahead of the outgoing argument area.
This should allow more variables & incoming arguments to be
- acceesed with unextended instructions. */
+ accessed with unextended instructions. */
if (frame_pointer_needed)
{
if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
value in GPRs is reported here. */
if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
> GP_ARG_NUM_REG)
- /* Fortunately, there are only two possibilites, the value
+ /* Fortunately, there are only two possibilities, the value
is either wholly in GPRs or half in GPRs and half not. */
part_mode = DImode;
}
/* The function returns a true if INSN is microcoded.
- Return false ptherwise. */
+ Return false otherwise. */
static bool
is_microcoded_insn (rtx insn)
return next_insn;
}
-/* Return whether the presence of INSN causes a dispatch group terminatation
+/* Return whether the presence of INSN causes a dispatch group termination
of group WHICH_GROUP.
If WHICH_GROUP == current_group, this function will return true if INSN
return false;
}
-/* Return true if it is recommended to keep NEXT_INSN "far" (in a seperate
+/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
static bool
one of the following schemes, depending on the value of the flag
-minsert_sched_nops = X:
(1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
- in order to force NEXT_INSN into a seperate group.
+ in order to force NEXT_INSN into a separate group.
(2) X < sched_finish_regroup_exact: insert exactly X nops.
GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
insertion (has a group just ended, how many vacant issue slots remain in the
;; Instruction definition to extend a 31-bit pointer into a 64-bit
-;; pointer. This is used for compatability.
+;; pointer. This is used for compatibility.
(define_expand "ptr_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
used to use the encodings 245..260, but that doesn't make sense:
PR_REG and PR_MEDIA_REG are actually the same register, and likewise
the FP registers stay the same when switching between compact and media
- mode. Hence, we also need to use the same dwarf frame coloumns.
+ mode. Hence, we also need to use the same dwarf frame columns.
Likewise, we need to support unwind information for SHmedia registers
even in compact code. */
#define SH_DBX_REGISTER_NUMBER(REGNO) \
"TARGET_TLS && TARGET_ARCH64"
"xor\\t%1, %%tle_lox10(%a2), %0")
-;; Now patterns combinding tldo_add{32,64} with some integer loads or stores
+;; Now patterns combining tldo_add{32,64} with some integer loads or stores
(define_insn "*tldo_ldub_sp32"
[(set (match_operand:QI 0 "register_operand" "=r")
(mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
{
int flags;
- /* Map explict sections into the appropriate attribute */
+ /* Map explicit sections into the appropriate attribute */
if (v850_get_data_area (decl) == DATA_AREA_NORMAL)
{
if (DECL_SECTION_NAME (decl))
return 0;
/* If the register is being pushed somewhere other than the stack
- space just aquired by the first operand then abandon this quest.
- Note: the test is <= becuase both values are negative. */
+ space just acquired by the first operand then abandon this quest.
+ Note: the test is <= because both values are negative. */
if (INTVAL (XEXP (plus, 1))
<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
return 0;
can appear in the "ghs section" pragma. These names are used to index
into the GHS_default_section_names[] and GHS_current_section_names[]
that are defined in v850.c, and so the ordering of each must remain
- consistant.
+ consistent.
These arrays give the default and current names for each kind of
section defined by the GHS pragmas. The current names can be changed
"TARGET_V850E && !TARGET_DISABLE_CALLT"
;; The CALLT instruction stores the next address of CALLT to CTPC register
;; without saving its previous value. So if the interrupt handler
- ;; or its caller could possibily execute the CALLT insn, save_interrupt
+ ;; or its caller could possibly execute the CALLT insn, save_interrupt
;; MUST NOT be called via CALLT.
"*
{
/* External interface */
/* Store in KEYP a value which can be passed to __gthread_setspecific/
- __gthread_getspecific to store and retrive a value which is
+ __gthread_getspecific to store and retrieve a value which is
specific to each calling thread. If DTOR is not NULL, it will be
called when a thread terminates with a non-NULL specific value for
this key, with the value as its sole argument. */
a comment showing where the end of the loop is. However, if there is a
label or a branch at the end of the loop then we need to place a nop
there. If the loop ends with a label we need the nop so that branches
- targetting that label will target the nop (and thus remain in the loop),
- instead of targetting the instruction after the loop (and thus exiting
+ targeting that label will target the nop (and thus remain in the loop),
+ instead of targeting the instruction after the loop (and thus exiting
the loop). If the loop ends with a branch, we need the nop in case the
- branch is targetting a location inside the loop. When the branch
+ branch is targeting a location inside the loop. When the branch
executes it will cause the loop count to be decremented even if it is
taken (because it is the last instruction in the loop), so we need to
nop after the branch to prevent the loop count from being decremented
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