* config/rs6000/spe.md (frob_di_df_2): Handle non-offsettable

	memory operand.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@118889 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c5ae49a..fed1fb5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2006-11-16  Joseph Myers  <joseph@codesourcery.com>
+
+       * config/rs6000/spe.md (frob_di_df_2): Handle non-offsettable
+       memory operand.
+
 2006-11-16  Richard Earnshaw  <rearnsha@arm.com>
 
        * arm.md (abssi2): Allow Thumb as well.  Use an SImode scratch for

diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 1ac1a84..f2410dd 100644 (file)
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -2223,6 +2223,11 @@
     case 0:
       return \"evmergehi %0,%1,%1\;mr %L0,%1\";
     case 1:
+      /* If the address is not offsettable we need to load the whole
+        doubleword into a 64-bit register and then copy the high word
+        to form the correct output layout.  */
+      if (!offsettable_nonstrict_memref_p (operands[1]))
+       return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
       /* If the low-address word is used in the address, we must load
        it last.  Otherwise, load it first.  Note that we cannot have
        auto-increment in that case since the address register is