2008-12-09 Andreas Krebbel <krebbel1@de.ibm.com>

	* config/s390/s390.md (movti, movdi_64, movdi_31,
	  *movsi_zarch, *movhi, *movqi, *mov<mode>_64, *mov<mode>_31,
	  *mov<mode>_64dfp, *mov<mode>_64, *mov<mode>_31, mov<mode>): Remove
	  Q->Q alternative.
	  (Integer->BLKmode splitter): Removed.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142583 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fe7ef41..b1a6993 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2008-12-09  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+       * config/s390/s390.md (movti, movdi_64, movdi_31,
+         *movsi_zarch, *movhi, *movqi, *mov<mode>_64, *mov<mode>_31,
+         *mov<mode>_64dfp, *mov<mode>_64, *mov<mode>_31, mov<mode>): Remove
+         Q->Q alternative.
+         (Integer->BLKmode splitter): Removed.
+
 2008-12-08  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/alpha/alpha.c (alpha_set_memflags): Process memory

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 2598039..1691fdb 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1081,17 +1081,16 @@
 ;
 
 (define_insn "movti"
-  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
-        (match_operand:TI 1 "general_operand" "QS,d,dPRT,d,Q"))]
+  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
+        (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
   "TARGET_64BIT"
   "@
    lmg\t%0,%N0,%S1
    stmg\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RSY,RSY,*,*,SS")
-   (set_attr "type" "lm,stm,*,*,*")])
+  [(set_attr "op_type" "RSY,RSY,*,*")
+   (set_attr "type" "lm,stm,*,*")])
 
 (define_split
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -1273,10 +1272,10 @@
 (define_insn "*movdi_64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
                             "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
-                             RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,?Q")
+                             RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
         (match_operand:DI 1 "general_operand"
                             "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
-                             d,*f,R,T,*f,*f,d,K,t,d,t,Q,?Q"))]
+                             d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
   "TARGET_64BIT"
   "@
    lghi\t%0,%h1
@@ -1304,16 +1303,15 @@
    #
    #
    stam\t%1,%N1,%S0
-   lam\t%0,%N0,%S1
-   #"
+   lam\t%0,%N0,%S1"
   [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
-                        RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,SS")
+                        RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
    (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
                      floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
-                     *,*,*")
+                     *,*")
    (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
                              z10,*,*,*,*,*,longdisp,*,longdisp,
-                             z10,z10,*,*,*,*,*")
+                             z10,z10,*,*,*,*")
    (set_attr "z10prop" "z10_fwd_A1,
                         z10_fwd_E1,
                         z10_fwd_E1,
@@ -1339,7 +1337,6 @@
                         *,
                         *,
                         *,
-                        *,
                         *")
 ])
 
@@ -1378,9 +1375,9 @@
 
 (define_insn "*movdi_31"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-                            "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,Q,d")
+                            "=d,d,Q,S,d   ,o,!*f,!*f,!*f,!R,!T,d")
         (match_operand:DI 1 "general_operand"
-                            " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,Q,b"))]
+                            " Q,S,d,d,dPRT,d, *f,  R,  T,*f,*f,b"))]
   "!TARGET_64BIT"
   "@
    lm\t%0,%N0,%S1
@@ -1394,11 +1391,10 @@
    ldy\t%0,%1
    std\t%1,%0
    stdy\t%1,%0
-   #
    #"
-  [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS,*")
-   (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*")
-   (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,*,z10")])
+  [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
+   (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
+   (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
 
 ; For a load from a symbol ref we can use one of the target registers
 ; together with larl to load the address.
@@ -1533,9 +1529,9 @@
 
 (define_insn "*movsi_zarch"
   [(set (match_operand:SI 0 "nonimmediate_operand"
-                           "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,?Q")
+                           "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
         (match_operand:SI 1 "general_operand"
-                           "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q,?Q"))]
+                           "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
   "TARGET_ZARCH"
   "@
    lhi\t%0,%h1
@@ -1559,10 +1555,9 @@
    stam\t%1,%1,%S0
    strl\t%1,%0
    mvhi\t%0,%1
-   lam\t%0,%0,%S1
-   #"
+   lam\t%0,%0,%S1"
   [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
-                        RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,SS")
+                        RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
    (set_attr "type" "*,
                      *,
                      *,
@@ -1584,10 +1579,9 @@
                      *,
                      larl,
                      *,
-                     *,
                      *")
    (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
-                             *,*,longdisp,*,longdisp,*,*,*,z10,z10,*,*")
+                             *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
    (set_attr "z10prop" "z10_fwd_A1,
                         z10_fwd_E1,
                         z10_fwd_E1,
@@ -1609,12 +1603,11 @@
                         *,
                         z10_rec,
                         z10_super,
-                        *,
                         *")])
 
 (define_insn "*movsi_esa"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
-        (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
+        (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
   "!TARGET_ZARCH"
   "@
    lhi\t%0,%h1
@@ -1627,10 +1620,9 @@
    ear\t%0,%1
    sar\t%0,%1
    stam\t%1,%1,%S0
-   lam\t%0,%0,%S1
-   #"
-  [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
-   (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")
+   lam\t%0,%0,%S1"
+  [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
+   (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
    (set_attr "z10prop" "z10_fwd_A1,
                         z10_fr_E1,
                         z10_fwd_A3,
@@ -1641,7 +1633,6 @@
                         z10_super_E1,
                         z10_super,
                         *,
-                        *,
                         *")
 ])
 
@@ -1752,8 +1743,8 @@
 })
 
 (define_insn "*movhi"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,?Q")
-        (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K,?Q"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
+        (match_operand:HI 1 "general_operand"      " d,n,R,T,b,d,d,d,K"))]
   ""
   "@
    lr\t%0,%1
@@ -1764,11 +1755,10 @@
    sth\t%1,%0
    sthy\t%1,%0
    sthrl\t%1,%0
-   mvhhi\t%0,%1
-   #"
-  [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,SS")
-   (set_attr "type"         "lr,*,*,*,larl,store,store,store,*,*")
-   (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,*")
+   mvhhi\t%0,%1"
+  [(set_attr "op_type"      "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
+   (set_attr "type"         "lr,*,*,*,larl,store,store,store,*")
+   (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
    (set_attr "z10prop" "z10_fr_E1,
                        z10_fwd_A1,
                        z10_super_E1,
@@ -1777,8 +1767,7 @@
                        z10_super,
                        z10_rec,
                        z10_rec,
-                       z10_super,
-                       *")])
+                       z10_super")])
 
 (define_peephole2
   [(set (match_operand:HI 0 "register_operand" "")
@@ -1813,8 +1802,8 @@
 })
 
 (define_insn "*movqi"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
-        (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
+        (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
   ""
   "@
    lr\t%0,%1
@@ -1824,10 +1813,9 @@
    stc\t%1,%0
    stcy\t%1,%0
    mvi\t%S0,%b1
-   mviy\t%S0,%b1
-   #"
-  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
-   (set_attr "type" "lr,*,*,*,store,store,store,store,*")
+   mviy\t%S0,%b1"
+  [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
+   (set_attr "type" "lr,*,*,*,store,store,store,store")
    (set_attr "z10prop" "z10_fr_E1,
                         z10_fwd_A1,
                         z10_super_E1,
@@ -1835,8 +1823,7 @@
                         z10_super,
                         z10_rec,
                         z10_super,
-                        z10_super,
-                        *")])
+                        z10_super")])
 
 (define_peephole2
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1905,8 +1892,8 @@
   "")
 
 (define_insn "*mov<mode>_64"
-  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o,Q")
-        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d,Q"))]
+  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS,  d,o")
+        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,QS, d,dRT,d"))]
   "TARGET_64BIT"
   "@
    lzxr\t%0
@@ -1916,23 +1903,21 @@
    lmg\t%0,%N0,%S1
    stmg\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*,*")])
+  [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
+   (set_attr "type"    "fsimptf,fsimptf,*,*,lm,stm,*,*")])
 
 (define_insn "*mov<mode>_31"
-  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,Q")
-        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f,Q"))]
+  [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
+        (match_operand:TD_TF 1 "general_operand"      " G,f,o,f"))]
   "!TARGET_64BIT"
   "@
    lzxr\t%0
    lxr\t%0,%1
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RRE,*,*,*")
-   (set_attr "type"    "fsimptf,fsimptf,*,*,*")])
+  [(set_attr "op_type" "RRE,RRE,*,*")
+   (set_attr "type"    "fsimptf,fsimptf,*,*")])
 
 ; TFmode in GPRs splitters
 
@@ -2023,9 +2008,9 @@
 
 (define_insn "*mov<mode>_64dfp"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
-                              "=f,f,f,d,f,f,R,T,d,d,RT,?Q")
+                              "=f,f,f,d,f,f,R,T,d, d,RT")
         (match_operand:DD_DF 1 "general_operand"
-                              "G,f,d,f,R,T,f,f,d,RT,d,?Q"))]
+                              " G,f,d,f,R,T,f,f,d,RT, d"))]
   "TARGET_64BIT && TARGET_DFP"
   "@
    lzdr\t%0
@@ -2038,11 +2023,10 @@
    stdy\t%1,%0
    lgr\t%0,%1
    lg\t%0,%1
-   stg\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+   stg\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
    (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
-                     fstoredf,fstoredf,lr,load,store,*")
+                     fstoredf,fstoredf,lr,load,store")
    (set_attr "z10prop" "*,
                         *,
                         *,
@@ -2053,13 +2037,12 @@
                         *,
                         z10_fr_E1,
                         z10_fwd_A3,
-                        z10_rec,
-                        *")
+                        z10_rec")
 ])
 
 (define_insn "*mov<mode>_64"
-  [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT,?Q")
-        (match_operand:DD_DF 1 "general_operand"       "G,f,R,T,f,f,d,RT, d,?Q"))]
+  [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
+        (match_operand:DD_DF 1 "general_operand"       "G,f,R,T,f,f,d,RT, d"))]
   "TARGET_64BIT"
   "@
    lzdr\t%0
@@ -2070,11 +2053,10 @@
    stdy\t%1,%0
    lgr\t%0,%1
    lg\t%0,%1
-   stg\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
+   stg\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
    (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
-                     fstore<mode>,fstore<mode>,lr,load,store,*")
+                     fstore<mode>,fstore<mode>,lr,load,store")
    (set_attr "z10prop" "*,
                         *,
                         *,
@@ -2083,14 +2065,13 @@
                         *,
                         z10_fr_E1,
                         z10_fwd_A3,
-                        z10_rec,
-                        *")])
+                        z10_rec")])
 
 (define_insn "*mov<mode>_31"
   [(set (match_operand:DD_DF 0 "nonimmediate_operand"
-                               "=f,f,f,f,R,T,d,d,Q,S,   d,o,Q")
+                               "=f,f,f,f,R,T,d,d,Q,S,   d,o")
         (match_operand:DD_DF 1 "general_operand"
-                               " G,f,R,T,f,f,Q,S,d,d,dPRT,d,Q"))]
+                               " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
   "!TARGET_64BIT"
   "@
    lzdr\t%0
@@ -2104,11 +2085,10 @@
    stm\t%1,%N1,%S0
    stmy\t%1,%N1,%S0
    #
-   #
    #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS")
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
    (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
-                     fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*,*")])
+                     fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
 
 (define_split
   [(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
@@ -2157,9 +2137,9 @@
 
 (define_insn "mov<mode>"
   [(set (match_operand:SD_SF 0 "nonimmediate_operand"
-                              "=f,f,f,f,R,T,d,d,d,R,T,?Q")
+                              "=f,f,f,f,R,T,d,d,d,R,T")
         (match_operand:SD_SF 1 "general_operand"
-                              " G,f,R,T,f,f,d,R,T,d,d,?Q"))]
+                              " G,f,R,T,f,f,d,R,T,d,d"))]
   ""
   "@
    lzer\t%0
@@ -2172,11 +2152,10 @@
    l\t%0,%1
    ly\t%0,%1
    st\t%1,%0
-   sty\t%1,%0
-   #"
-  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
+   sty\t%1,%0"
+  [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
    (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>,
-                     fstore<mode>,fstore<mode>,lr,load,load,store,store,*")
+                     fstore<mode>,fstore<mode>,lr,load,load,store,store")
    (set_attr "z10prop" "*,
                         *,
                         *,
@@ -2187,8 +2166,7 @@
                         z10_fwd_A3,
                         z10_fwd_A3,
                         z10_super,
-                        z10_rec,
-                        *")])
+                        z10_rec")])
 
 ;
 ; movcc instruction pattern
@@ -2222,21 +2200,6 @@
   "mvc\t%O0(%2,%R0),%S1"
   [(set_attr "op_type" "SS")])
 
-(define_split
-  [(set (match_operand 0 "memory_operand" "")
-        (match_operand 1 "memory_operand" ""))]
-  "reload_completed
-   && GET_MODE (operands[0]) == GET_MODE (operands[1])
-   && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
-  [(parallel
-    [(set (match_dup 0) (match_dup 1))
-     (use (match_dup 2))])]
-{
-  operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
-  operands[0] = adjust_address (operands[0], BLKmode, 0);
-  operands[1] = adjust_address (operands[1], BLKmode, 0);
-})
-
 (define_peephole2
   [(parallel
     [(set (match_operand:BLK 0 "memory_operand" "")