* config/m68hc11/m68hc11.md ("*lshrsi3_const"): Disable for 68HC12.

	("*lshrsi3"): Also accept an immediate for 68HC12.
	("*ashrsi3_const"): Likewise.
	("*ashrsi3"): Likewise.
	("*ashlsi3_const"): Likewise.
	("*ashlsi3"): Likewise.
	("cmphi_1_hc12"): Compare two hard register by pushing them and
	comparing with a pop; don't use a split for that.
	("cmphi split"): Disable compare split for 68HC12.

	* config/m68hc11/m68hc11.c (m68hc11_notice_update_cc): Invalidate
	the status operands if they have side effects.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@79068 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 62502e6..dc730ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2004-03-07  Stephane Carrez  <stcarrez@nerim.fr>
+
+       * config/m68hc11/m68hc11.md ("*lshrsi3_const"): Disable for 68HC12.
+       ("*lshrsi3"): Also accept an immediate for 68HC12.
+       ("*ashrsi3_const"): Likewise.
+       ("*ashrsi3"): Likewise.
+       ("*ashlsi3_const"): Likewise.
+       ("*ashlsi3"): Likewise.
+       ("cmphi_1_hc12"): Compare two hard register by pushing them and
+       comparing with a pop; don't use a split for that.
+       ("cmphi split"): Disable compare split for 68HC12.
+
+       * config/m68hc11/m68hc11.c (m68hc11_notice_update_cc): Invalidate
+       the status operands if they have side effects.
+
 2004-03-07  Kazu Hirata  <kazu@cs.umass.edu>
 
        * defaults.h (LEGITIMIZE_ADDRESS): Provide a default

diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 9fb9060..e4bd72a 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -4082,6 +4082,12 @@ m68hc11_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED)
       && cc_status.value2
       && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
     cc_status.value2 = 0;
+
+  else if (cc_status.value1 && side_effects_p (cc_status.value1))
+    cc_status.value1 = 0;
+
+  else if (cc_status.value2 && side_effects_p (cc_status.value2))
+    cc_status.value2 = 0;
 }
 
 /* The current instruction does not affect the flags but changes

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index 08d03cb..5e6bc23 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -308,7 +308,7 @@
   [(set (cc0)
        (compare (match_operand:HI 0 "hard_reg_operand" "")
                 (match_operand:HI 1 "hard_reg_operand" "")))]
-  "TARGET_M6812
+  "0 && TARGET_M6812
    && reload_completed && !(Z_REG_P (operands[0]) || Z_REG_P (operands[1]))"
   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
    (set (cc0)
@@ -344,8 +344,10 @@
       cc_status.flags |= CC_REVERSED;
       return \"cp%1\\t%0\";
     }
+  else if (SP_REG_P (operands[1]))
+    return \"sts\\t2,-sp\n\\tcp%0\\t2,sp+\";
   else if (H_REG_P (operands[1]))
-    return \"#\";
+    return \"psh%1\n\\tcp%0\\t2,sp+\";
   else
     return \"cp%0\\t%1\";
 }")
@@ -4615,10 +4617,10 @@
    "")
 
 (define_insn "*ashlsi3_const1"
-  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u")
-       (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u")
+  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u,*u")
+       (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u,m")
                   (const_int 1)))
-   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d"))]
+   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d,&d"))]
    ""
    "*
 {
@@ -4674,7 +4676,7 @@
        (ashift:SI (match_dup 0)
                   (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *ashlsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -4684,7 +4686,7 @@
 (define_insn "*ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
        (ashift:SI (match_dup 0)
-                  (match_operand:HI 1 "general_operand" "y,m")))
+                  (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -4697,7 +4699,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];
@@ -5084,7 +5091,7 @@
        (ashiftrt:SI (match_dup 0)
                     (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *ashrsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -5094,7 +5101,7 @@
 (define_insn "*ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
        (ashiftrt:SI (match_dup 0)
-                    (match_operand:HI 1 "general_operand" "y,m")))
+                    (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -5106,7 +5113,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];
@@ -5367,10 +5379,10 @@
     #")
 
 (define_insn "*lshrsi3_const1"
-  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u")
-       (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u")
+  [(set (match_operand:SI 0 "non_push_operand" "=D,D,D,m,*u,*u")
+       (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,*u,m,*u,m")
                     (const_int 1)))
-   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d"))]
+   (clobber (match_scratch:HI 2 "=X,X,X,&d,&d,&d"))]
    ""
    "*
 {
@@ -5421,7 +5433,7 @@
        (lshiftrt:SI (match_dup 0)
                     (match_operand:HI 1 "const_int_operand" "")))
    (clobber (match_scratch:HI 2 "=y"))]
-   ""
+   "TARGET_M6811 /* See *lshrsi3 note.  */"
    "*
 {
   CC_STATUS_INIT;
@@ -5431,7 +5443,7 @@
 (define_insn "*lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "+D,D")
        (lshiftrt:SI (match_dup 0)
-                    (match_operand:HI 1 "general_operand" "y,m")))
+                    (match_operand:HI 1 "general_operand" "y,mi")))
    (clobber (match_scratch:HI 2 "=1,X"))]
    ""
    "*
@@ -5443,7 +5455,12 @@
      is not enough register in class A_REGS.
 
      Assuming that 'operands[1]' does not refer to the stack (which 
-     is true for 68hc11 only, we save temporary the value of Y.  */
+     is true for 68hc11 only, we save temporary the value of Y.
+
+     For 68HC12 we must also accept a constant because Z register is
+     disabled when compiling with -fomit-frame-pointer.  We can come up
+     with a reload problem and the *lshrsi3_const pattern was disabled
+     for that reason.  */
   if (!Y_REG_P (operands[2]))
     {
       rtx ops[1];