Backport from mainline:

	2013-03-27  Walter Lee  <walt@tilera.com>

	* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
	input operands.
	(insn_v1mulus): Ditto.
	(insn_v2muls): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@197148 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 67486f4..21f6341 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -3,6 +3,16 @@
        Backport from mainline:
        2013-03-27  Walter Lee  <walt@tilera.com>
 
+       * config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
+       input operands.
+       (insn_v1mulus): Ditto.
+       (insn_v2muls): Ditto.
+
+2013-03-27  Walter Lee  <walt@tilera.com>
+
+       Backport from mainline:
+       2013-03-27  Walter Lee  <walt@tilera.com>
+
        * config/tilegx/tilegx.h (ASM_OUTPUT_ADDR_VEC_ELT): Delete
        extra tab.
        (ASM_OUTPUT_ADDR_DIFF_ELT): Ditto.

diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index ff845ae..5a16fec 100644 (file)
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -4508,8 +4508,8 @@
 
 (define_expand "insn_v1mulu"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
@@ -4538,8 +4538,8 @@
 
 (define_expand "insn_v1mulus"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
@@ -4566,8 +4566,8 @@
 
 (define_expand "insn_v2muls"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,