A standalone __builtin_rx_sat isn't implementable due to needing
to keep the flags live before reload. Instead provide a saturating
add pattern, which hopefully will be pattern-matched by high-level
optimizations.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168928
138bc75d-0d04-0410-961f-
82ee72b054a4
2011-01-17 Richard Henderson <rth@redhat.com>
+ * config/rx/rx.c (RX_BUILTIN_SAT): Remove.
+ (rx_init_builtins): Remove sat builtin.
+ (rx_expand_builtin): Likewise.
+ * config/rx/rx.md (ssaddsi3): New.
+ (*sat): Rename from sat. Represent the CC_REG input.
+
* config/rx/predicates.md (rshift_operator): New.
* config/rx/rx.c (rx_expand_insv): Remove.
* config/rx/rx-protos.h: Update.
RX_BUILTIN_REVW,
RX_BUILTIN_RMPA,
RX_BUILTIN_ROUND,
- RX_BUILTIN_SAT,
RX_BUILTIN_SETPSW,
RX_BUILTIN_WAIT,
RX_BUILTIN_max
ADD_RX_BUILTIN1 (RACW, "racw", void, integer);
ADD_RX_BUILTIN1 (ROUND, "round", intSI, float);
ADD_RX_BUILTIN1 (REVW, "revw", intSI, intSI);
- ADD_RX_BUILTIN1 (SAT, "sat", intSI, intSI);
ADD_RX_BUILTIN1 (WAIT, "wait", void, void);
}
case RX_BUILTIN_ROUND: return rx_expand_builtin_round (op, target);
case RX_BUILTIN_REVW: return rx_expand_int_builtin_1_arg
(op, target, gen_revw, false);
- case RX_BUILTIN_SAT: return rx_expand_int_builtin_1_arg
- (op, target, gen_sat, false);
case RX_BUILTIN_WAIT: emit_insn (gen_wait ()); return NULL_RTX;
default:
[(set_attr "length" "3,2,3")]
)
+;; Saturate to 32-bits
+(define_insn_and_split "ssaddsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "rx_source_operand" "riQ")))
+ (clobber (reg:CC CC_REG))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:SI (match_dup 1) (match_dup 2)))
+ (set (reg:CC_ZSC CC_REG)
+ (compare:CC_ZSC
+ (plus:SI (match_dup 1) (match_dup 2))
+ (const_int 0)))])
+ (set (match_dup 0)
+ (unspec:SI [(match_dup 0) (reg:CC CC_REG)]
+ UNSPEC_BUILTIN_SAT))]
+ ""
+)
+
+(define_insn "*sat"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "0")
+ (reg:CC CC_REG)]
+ UNSPEC_BUILTIN_SAT))]
+ "reload_completed"
+ "sat\t%0"
+ [(set_attr "length" "2")]
+)
+
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
(set_attr "length" "3,5")]
)
-;; Saturate to 32-bits
-(define_insn "sat"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
- UNSPEC_BUILTIN_SAT))]
- ""
- "sat\t%0"
- [(set_attr "length" "2")]
-)
-
;;---------- Control Registers ------------------------
;; Clear Processor Status Word