void I8253::initialize()
{
- DEVICE::initialize();
- __HAS_I8254 = osd->check_feature(_T("HAS_I8254"));
for(int ch = 0; ch < 3; ch++) {
counter[ch].prev_out = true;
counter[ch].prev_in = false;
counter[ch].low_write = counter[ch].high_write = false;
counter[ch].delay = false;
counter[ch].start = false;
-//#ifdef HAS_I8254
- if(__HAS_I8254) {
- // 8254 read-back command
- counter[ch].null_count = true;
- counter[ch].status_latched = false;
- } else {
- counter[ch].null_count = false;
- counter[ch].status_latched = false;
- }
-//#endif
+#ifdef HAS_I8254
+ // 8254 read-back command
+ counter[ch].null_count = true;
+ counter[ch].status_latched = false;
+#endif
}
}
}
counter[ch].high_write = false;
}
-//#ifdef HAS_I8254
- if(__HAS_I8254) counter[ch].null_count = true;
-//#endif
+#ifdef HAS_I8254
+ counter[ch].null_count = true;
+#endif
// set signal
if(counter[ch].mode == 0) {
set_signal(ch, false);
case 3: // ctrl reg
if((data & 0xc0) == 0xc0) {
-//#ifdef HAS_I8254
- if(!__HAS_I8254) break;
+#ifdef HAS_I8254
// i8254 read-back command
for(ch = 0; ch < 3; ch++) {
uint8_t bit = 2 << ch;
latch_count(ch);
}
}
-//#endif
+#endif
break;
}
ch = (data >> 6) & 3;
stop_count(ch);
counter[ch].count_reg = 0;
// }
-//#ifdef HAS_I8254
- if(__HAS_I8254) counter[ch].null_count = true;
-//#endif
+#ifdef HAS_I8254
+ counter[ch].null_count = true;
+#endif
} else if(!counter[ch].count_latched) {
latch_count(ch);
}
case 0:
case 1:
case 2:
-//#ifdef HAS_I8254
- if((__HAS_I8254) && (counter[ch].status_latched)) {
+#ifdef HAS_I8254
+ if(counter[ch].status_latched) {
counter[ch].status_latched = false;
return counter[ch].status;
}
-//#endif
+#endif
// if not latched, through current count
if(!counter[ch].count_latched) {
if(!counter[ch].low_read && !counter[ch].high_read) {
clock -= 1;
counter[ch].delay = false;
counter[ch].count = COUNT_VALUE(ch);
-//#ifdef HAS_I8254
- if(__HAS_I8254) counter[ch].null_count = false;
-//#endif
+#ifdef HAS_I8254
+ counter[ch].null_count = false;
+#endif
}
// update counter
if(counter[ch].count <= 0) {
if(counter[ch].mode == 0 || counter[ch].mode == 2 || counter[ch].mode == 3) {
counter[ch].count += tmp;
-//#ifdef HAS_I8254
- if(__HAS_I8254) counter[ch].null_count = false;
-//#endif
+#ifdef HAS_I8254
+ counter[ch].null_count = false;
+#endif
goto loop;
} else {
counter[ch].start = false;
state_fio->FputInt32(counter[i].mode);
state_fio->FputBool(counter[i].delay);
state_fio->FputBool(counter[i].start);
-//#ifdef HAS_I8254
- if(__HAS_I8254) {
- state_fio->FputBool(counter[i].null_count);
- state_fio->FputBool(counter[i].status_latched);
- state_fio->FputUint8(counter[i].status);
- }
-//#endif
+#ifdef HAS_I8254
+ state_fio->FputBool(counter[i].null_count);
+ state_fio->FputBool(counter[i].status_latched);
+ state_fio->FputUint8(counter[i].status);
+#endif
state_fio->FputUint64(counter[i].freq);
state_fio->FputInt32(counter[i].register_id);
state_fio->FputUint32(counter[i].input_clk);
counter[i].mode = state_fio->FgetInt32();
counter[i].delay = state_fio->FgetBool();
counter[i].start = state_fio->FgetBool();
-//#ifdef HAS_I8254
- if(__HAS_I8254) {
- counter[i].null_count = state_fio->FgetBool();
- counter[i].status_latched = state_fio->FgetBool();
- counter[i].status = state_fio->FgetUint8();
- }
-//#endif
+#ifdef HAS_I8254
+ counter[i].null_count = state_fio->FgetBool();
+ counter[i].status_latched = state_fio->FgetBool();
+ counter[i].status = state_fio->FgetUint8();
+#endif
counter[i].freq = state_fio->FgetUint64();
counter[i].register_id = state_fio->FgetInt32();
counter[i].input_clk = state_fio->FgetUint32();
}
register_event(this, EVENT_TIMER, 100000, false, &timer_id);
}
- if(modereg & 4) {
- d_fdc->write_signal(SIG_UPD765A_MOTOR, data, 0x08);
- }
+// if(modereg & 4) {
+// d_fdc->write_signal(SIG_UPD765A_MOTOR, data, 0x08);
+// }
ctrlreg = data;
}
break;
d_fdc->set_drive_type(0, DRIVE_TYPE_2DD);
d_fdc->set_drive_type(1, DRIVE_TYPE_2DD);
}
- if(((data & 4) == 0) && (((modereg & 1) != 0) || ((data & 1) != 0))) {
- d_fdc->write_signal(SIG_UPD765A_MOTOR, 0x01, 0x01);
- }
modereg = data;
break;
#endif
}
break;
case SIG_FLOPPY_DRQ:
- if(ctrlreg & 0x04) {
- if(modereg & 1) {
- d_dma->write_signal(SIG_I8237_CH2, data, mask);
- } else {
- d_dma->write_signal(SIG_I8237_CH3, data, mask);
- }
+ if(modereg & 1) {
+ d_dma->write_signal(SIG_I8237_CH2, data, mask);
+ } else {
+ d_dma->write_signal(SIG_I8237_CH3, data, mask);
}
break;
#endif
{
itf = NULL;
ipl = NULL;
- itf_bank = PC98_ITF_ITF;
+ itf_bank = PC98_ITF_IPL;
}
ITF::~ITF()
void ITF::reset(void)
{
- itf_bank = PC98_ITF_ITF;
+ itf_bank = PC98_ITF_IPL;
}
// See: http://www.webtech.co.jp/company/doc/undocumented_mem/io_mem.txt .
void ITF::write_io8(uint32_t addr, uint32_t data)
{
- switch(addr & 0x1) {
+ switch(addr & 0x3) {
case 0x1:
+#if 0
printf("SET %05x %02x\n", addr, data);
if((data & 0xff) == 0x10) {
#if defined(_PCH98S)
itf_bank = PC98_ITF_ITF;
}
#endif
+#else
+ // From MAME0185
+ if(((data & 0xf0) == 0x00) || ((data & 0xf0) == 0x10)) {
+ if((data & 0xed) == 0x00) {
+ if((data & 0x02) == 0) {
+ itf_bank = PC98_ITF_ITF;
+ } else {
+ itf_bank = PC98_ITF_IPL;
+ }
+ }
+ }
+
+#endif
break;
default:
break;
{
uint32_t raddr = addr & 0xfffff;
// ToDo: Address with i286/i386/i486.
- //if(raddr < 0xe8000) return 0xff; // OK?
+ if(raddr < 0xe8000) return 0xff; // OK?
switch(itf_bank) {
case PC98_ITF_IPL:
if(ipl == NULL) return 0xff;
break;
case PC98_ITF_ITF:
if(itf == NULL) return 0xff;
- raddr = raddr & 0x7fff;
- printf("DATA: %05x %02x\n", addr, itf[raddr]);
- return itf[raddr];
+// printf("%05x\n", raddr);
+ if(raddr < 0xf8000) return 0xff;
+ //printf("DATA: %05x %02x\n", addr, itf[raddr]);
+ return itf[raddr & 0x7fff];
break;
#if defined(_PCH98S)
case PC98_ITF_ITF: