FAIL;
else
operands[2] = force_reg (SImode, operands[2]);
+
if (! TARGET_POWER && ! TARGET_POWERPC)
{
emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
- (match_operand:SF 2 "reg_or_short_operand" "")))
+ (match_operand:SF 2 "gpc_reg_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
"TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(define_split
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
- (match_operand:SF 2 "reg_or_short_operand" "")))
+ (match_operand:SF 2 "gpc_reg_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
"TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
- (match_operand:DF 2 "reg_or_short_operand" "")))
+ (match_operand:DF 2 "gpc_reg_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
"TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(define_split
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
- (match_operand:DF 2 "reg_or_short_operand" "")))
+ (match_operand:DF 2 "gpc_reg_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
"TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(define_insn "muldi3"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
- (match_operand:DI 2 "reg_or_short_operand" "r")))]
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC64"
"mulld %0,%1,%2"
[(set_attr "type" "imul")])
sd%U0%X0 %1,%0
#
fmr %0,%1
- lfd %0,%1
+ lfd%U1%X1 %0,%1
stfd%U0%X0 %1,%0"
[(set_attr "type" "*,load,*,*,fp,fpload,*")])
\f