PR target/34702

	* doc/invoke.texi (i386 and x86-64 Options) [mrecip]: Document
	limitations of reciprocal sequences on x86 targets.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@131394 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 903656c..42648c8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2008-01-08  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/34702
+       * doc/invoke.texi (i386 and x86-64 Options) [mrecip]: Document
+       limitations of reciprocal sequences on x86 targets.
+
 2008-01-08  Richard Guenther  <rguenther@suse.de>
 
        PR tree-optimization/34683
@@ -15,9 +21,9 @@
        * config/i386/i386.md (neg<mode>2): Rename from negsf2, negdf2 and
        negxf2.  Macroize expander using X87MODEF mode iterator.  Change
        predicates of op0 and op1 to register_operand.
-       (abs<mode>2): Rename from abssf2, absdf2 and negxf2.  Macroize expander
-       using X87MODEF mode iterator.  Change predicates of op0 and op1 to
-       register_operand.
+       (abs<mode>2): Rename from abssf2, absdf2 and negxf2.  Macroize
+       expander using X87MODEF mode iterator.  Change predicates of
+       op0 and op1 to register_operand.
        ("*absneg<mode>2_mixed", "*absneg<mode>2_sse"): Rename from
        corresponding patterns and macroize using MODEF macro.  Change
        predicates of op0 and op1 to register_operand and remove
@@ -32,7 +38,7 @@
        * config/i386/sse.md (negv4sf2, absv4sf2, neg2vdf2, absv2df2):
        Change predicate of op1 to register_operand.
        * config/i386/i386.c (ix86_expand_fp_absneg_operator): Remove support
-       for memory operands.2008-01-07  Richard Guenther  <rguenther@suse.de>
+       for memory operands.
 
 2008-01-07  Nathan Froyd  <froydnj@codesourcery.com>
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a1161d3..b48ba2e 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -10647,9 +10647,14 @@ or @code{remainder} built-in functions: see @ref{Other Builtins} for details.
 @item -mrecip
 @opindex mrecip
 This option will enable GCC to use RCPSS and RSQRTSS instructions (and their
-vectorized variants RCPPS and RSQRTPS) instead of DIVSS and SQRTSS (and their
-vectorized variants).  These instructions will be generated only when
-@option{-funsafe-math-optimizations} is enabled.
+vectorized variants RCPPS and RSQRTPS) with additional Newton-Rhapson step
+to increase precision instead of DIVSS and SQRTSS (and their vectorized
+variants) for single precision floating point arguments.  These instructions
+are generated only when @option{-funsafe-math-optimizations} is enabled
+together with @option{-finite-math-only} and @option{-fno-trapping-math}.
+Note that while the throughput of the sequence is higher than the throughput
+of the non-reciprocal instruction, the precision of the sequence can be
+decreased up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
 
 @item -mveclibabi=@var{type}
 @opindex mveclibabi