}
/* Determine if there is an opportunity for a bypass optimization.
- Bypass suceeds on the 960K* if the destination of the previous
+ Bypass succeeds on the 960K* if the destination of the previous
instruction is the second operand of the current instruction.
Bypass always succeeds on the C*.
}
\f
/* Do any needed setup for a varargs function. For the i960, we must
- create a register paramter block if one doesn't exist, and then copy
+ create a register parameter block if one doesn't exist, and then copy
all register parameters to memory. */
void
[(set_attr "type" "branch")])
\f
;; Normal move instructions.
-;; This code is based on the sparc machine desciption.
+;; This code is based on the sparc machine description.
(define_expand "movsi"
[(set (match_operand:SI 0 "general_operand" "")
union {double d; int i[2];} u;
register double d;
- /* fmovecr must be emulated on the 68040, so it shoudn't be used at all. */
+ /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
if (TARGET_68040)
return 0;
/* EQ tests are usually false and NE tests are usually true. Also,
most quantities are positive, so we can make the appropriate guesses
- about signed comparisons against zero. Consider unsigned comparsions
+ about signed comparisons against zero. Consider unsigned comparisons
to be a range check and assume quantities to be in range. */
switch (GET_CODE (condition))
{
spill area instead of memory.
-waste if only used once
- floating point caluclations
+ floating point calculations
-probably a waste unless we have run out of general purpose registers
freeing up general purpose registers
But this is currently disabled since tying in global_alloc is not
yet implemented.
- The explaination of why the preserved register is not used is as follows,
- I believe. The registers are being allocated in order. Tieing is not
+ The explanation of why the preserved register is not used is as follows,
+ I believe. The registers are being allocated in order. Tying is not
done so efficiently, so when it comes time to do the first allocation,
there are no registers left to use without spilling except extended
registers. Then when the next pseudo register needs a hard reg, there
The following follows the current 88open UCS specification for the
Extended Register File (XRF):
Reg 32 = x0 Always equal to zero
- Reg 33-53 = x1-x21 Tempory registers (Caller Save)
+ Reg 33-53 = x1-x21 Temporary registers (Caller Save)
Reg 54-61 = x22-x29 Preserver registers (Callee Save)
Reg 62-63 = x30-x31 Reserved for future ABI use.
/* Definitions of target machine for GNU compiler.
- Motorola m88100 running the AT&T/Unisoft/Motorla V.3 reference port.
+ Motorola m88100 running the AT&T/Unisoft/Motorola V.3 reference port.
Copyright (C) 1990, 1991 Free Software Foundation, Inc.
Contributed by Ray Essick (ressick@mot.com)
Currently supported by Tom Wood (wood@dg-rtp.dg.com)
rtx cmp0; /* first operand to compare */
rtx cmp1; /* second operand to compare */
int *p_invert; /* NULL or ptr to hold whether branch needs */
- /* to reserse it's test */
+ /* to reverse its test */
{
struct cmp_info {
enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
return (rtx)0;
}
- /* allocate a psuedo to calculate the value in. */
+ /* allocate a pseudo to calculate the value in. */
result = gen_reg_rtx (SImode);
}
static rtx
block_move_load_store (dest_reg, src_reg, p_bytes, p_offset, align, orig_src)
- rtx src_reg; /* register holding source memory addresss */
- rtx dest_reg; /* register holding dest. memory addresss */
+ rtx src_reg; /* register holding source memory address */
+ rtx dest_reg; /* register holding dest. memory address */
int *p_bytes; /* pointer to # bytes remaining */
int *p_offset; /* pointer to current offset */
int align; /* alignment */
# PREMADE_ATTRTAB = $(srcdir)/config/mips-at.c
# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips-at.md
-# Supress building libgcc1.a, since the MIPS compiler port is complete
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
# and does not need anything from libgcc1.a.
LIBGCC1 = libgcc1.null
# PREMADE_ATTRTAB = $(srcdir)/config/mips-at.c
# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips-at.md
-# Supress building libgcc1.a, since the MIPS compiler port is complete
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
# and does not need anything from libgcc1.a.
LIBGCC1 = libgcc1.null
# PREMADE_ATTRTAB = $(srcdir)/config/mips-at.c
# PREMADE_ATTRTAB_MD = $(srcdir)/config/mips-at.md
-# Supress building libgcc1.a, since the MIPS compiler port is complete
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
# and does not need anything from libgcc1.a.
LIBGCC1 = libgcc1.null
#define SCCS_DIRECTIVE
-/* LINK_SPEC is needed only for Sunos 4. */
+/* LINK_SPEC is needed only for SunOS 4. */
#undef LINK_SPEC
}
/* If it's the stack or frame pointer, check offset alignment.
- We can have improper aligment in the function entry code. */
+ We can have improper alignment in the function entry code. */
if (base
&& (REGNO (base) == FRAME_POINTER_REGNUM
|| REGNO (base) == STACK_POINTER_REGNUM))
}
/* Output assembler code to perform a quadword move insn
- with operands OPERANDS. This is very similar to the preceeding
+ with operands OPERANDS. This is very similar to the preceding
output_move_double function. */
char *
if (reg1 != REGNO (XEXP (addr2, 0)))
return 0;
- /* The first offset must be evenly divisable by 8 to ensure the
+ /* The first offset must be evenly divisible by 8 to ensure the
address is 64 bit aligned. */
if (offset1 % 8 != 0)
return 0;
/* We redefine this because there is a hidden variable on the stack
that VAXC$ESTABLISH uses. We just need to add four bytes to whatever
- gcc thinks that we need. Similarily, we need to move all local variables
+ gcc thinks that we need. Similarly, we need to move all local variables
down 4 bytes in the stack. */
#define STARTING_FRAME_OFFSET -4
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