#define THUMB2_LOAD_BIT 0x00100000
#define BAD_ARGS _("bad arguments to instruction")
+#define BAD_SP _("r13 not allowed here")
#define BAD_PC _("r15 not allowed here")
#define BAD_COND _("instruction cannot be conditional")
#define BAD_OVERLAP _("registers may not be the same")
unwind.personality_index = -1;
unwind.frame_size = 0;
unwind.fp_offset = 0;
- unwind.fp_reg = 13;
+ unwind.fp_reg = REG_SP;
unwind.fp_used = 0;
unwind.sp_restored = 0;
}
demand_empty_rest_of_line ();
- if (sp_reg != 13 && sp_reg != unwind.fp_reg)
+ if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
{
as_bad (_("register must be either sp or set by a previous"
"unwind_movsp directive"));
/* Don't generate any opcodes, just record the information for later. */
unwind.fp_reg = fp_reg;
unwind.fp_used = 1;
- if (sp_reg == 13)
+ if (sp_reg == REG_SP)
unwind.fp_offset = unwind.frame_size - offset;
else
unwind.fp_offset -= offset;
} \
} while (0)
+/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
+ instructions are unpredictable if these registers are used. This
+ is the BadReg predicate in ARM's Thumb-2 documentation. */
+#define reject_bad_reg(reg) \
+ do \
+ if (reg == REG_SP || reg == REG_PC) \
+ { \
+ inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
+ return; \
+ } \
+ while (0)
+
/* Functions for operand encoding. ARM, then Thumb. */
#define rotate_left(v, n) (v << n | v >> (32 - n))
static void
do_co_reg (void)
{
+ unsigned Rd;
+
+ Rd = inst.operands[2].reg;
+ if (thumb_mode)
+ {
+ if (inst.instruction == 0xee000010
+ || inst.instruction == 0xfe000010)
+ /* MCR, MCR2 */
+ reject_bad_reg (Rd);
+ else
+ /* MRC, MRC2 */
+ constraint (Rd == REG_SP, BAD_SP);
+ }
+ else
+ {
+ /* MCR */
+ if (inst.instruction == 0xe000010)
+ constraint (Rd == REG_PC, BAD_PC);
+ }
+
+
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 21;
- inst.instruction |= inst.operands[2].reg << 12;
+ inst.instruction |= Rd << 12;
inst.instruction |= inst.operands[3].reg << 16;
inst.instruction |= inst.operands[4].reg;
inst.instruction |= inst.operands[5].imm << 5;
static void
do_co_reg2c (void)
{
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[2].reg;
+ Rn = inst.operands[3].reg;
+
+ if (thumb_mode)
+ {
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ }
+ else
+ {
+ constraint (Rd == REG_PC, BAD_PC);
+ constraint (Rn == REG_PC, BAD_PC);
+ }
+
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].imm << 4;
- inst.instruction |= inst.operands[2].reg << 12;
- inst.instruction |= inst.operands[3].reg << 16;
+ inst.instruction |= Rd << 12;
+ inst.instruction |= Rn << 16;
inst.instruction |= inst.operands[4].reg;
}
if (inst.operands[0].present)
{
reg = inst.operands[0].reg;
- constraint (reg != 13, _("SRS base register must be r13"));
+ constraint (reg != REG_SP, _("SRS base register must be r13"));
}
else
- reg = 13;
+ reg = REG_SP;
inst.instruction |= reg << 16;
inst.instruction |= inst.operands[1].imm;
Rd = inst.operands[0].reg;
Rn = inst.operands[1].reg;
- constraint (Rd == 15, _("PC not allowed as destination"));
+ /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
+ SP-{plus,minute}-immediate form of the instruction. */
+ reject_bad_reg (Rd);
+
inst.instruction |= (Rn << 16) | (Rd << 8);
inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
}
{
int add;
+ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
+
add = (inst.instruction == T_MNEM_add
|| inst.instruction == T_MNEM_adds);
opcode = 0;
{
if (Rd == REG_PC)
{
+ constraint (add, BAD_PC);
constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
_("only SUBS PC, LR, #const allowed"));
constraint (inst.reloc.exp.X_op != O_constant,
}
}
}
+
+ constraint (Rd == REG_PC, BAD_PC);
+ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
+ constraint (Rs == REG_PC, BAD_PC);
+ reject_bad_reg (Rn);
+
/* If we get here, it can't be done in 16 bits. */
constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
_("shift must be constant"));
static void
do_t_adr (void)
{
- if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
+ unsigned Rd;
+
+ Rd = inst.operands[0].reg;
+ reject_bad_reg (Rd);
+
+ if (unified_syntax && inst.size_req == 0 && Rd <= 7)
{
/* Defer to section relaxation. */
inst.relax = inst.instruction;
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << 4;
+ inst.instruction |= Rd << 4;
}
else if (unified_syntax && inst.size_req != 2)
{
/* Generate a 32-bit opcode. */
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << 8;
+ inst.instruction |= Rd << 8;
inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
inst.reloc.pc_rel = 1;
}
inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
inst.reloc.pc_rel = 1;
- inst.instruction |= inst.operands[0].reg << 4;
+ inst.instruction |= Rd << 4;
}
}
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
Rn = inst.operands[2].reg;
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rs);
+ if (inst.operands[2].isreg)
+ reject_bad_reg (Rn);
+
if (unified_syntax)
{
if (!inst.operands[2].isreg)
? inst.operands[1].reg /* Rd, Rs, foo */
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
Rn = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rs);
+ if (inst.operands[2].isreg)
+ reject_bad_reg (Rn);
if (unified_syntax)
{
static void
do_t_bfc (void)
{
+ unsigned Rd;
unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
constraint (msb > 32, _("bit-field extends past end of register"));
/* The instruction encoding stores the LSB and MSB,
not the LSB and width. */
- inst.instruction |= inst.operands[0].reg << 8;
+ Rd = inst.operands[0].reg;
+ reject_bad_reg (Rd);
+ inst.instruction |= Rd << 8;
inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
inst.instruction |= msb - 1;
static void
do_t_bfi (void)
{
+ int Rd, Rn;
unsigned int msb;
+ Rd = inst.operands[0].reg;
+ reject_bad_reg (Rd);
+
/* #0 in second position is alternative syntax for bfc, which is
the same instruction but with REG_PC in the Rm field. */
if (!inst.operands[1].isreg)
- inst.operands[1].reg = REG_PC;
+ Rn = REG_PC;
+ else
+ {
+ Rn = inst.operands[1].reg;
+ reject_bad_reg (Rn);
+ }
msb = inst.operands[2].imm + inst.operands[3].imm;
constraint (msb > 32, _("bit-field extends past end of register"));
/* The instruction encoding stores the LSB and MSB,
not the LSB and width. */
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
inst.instruction |= msb - 1;
static void
do_t_bfx (void)
{
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+
constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
_("bit-field extends past end of register"));
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
inst.instruction |= inst.operands[3].imm - 1;
{
constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
if (inst.operands[0].isreg)
- /* We have a register, so this is BLX(2). */
- inst.instruction |= inst.operands[0].reg << 3;
+ {
+ constraint (inst.operands[0].reg == REG_PC, BAD_PC);
+ /* We have a register, so this is BLX(2). */
+ inst.instruction |= inst.operands[0].reg << 3;
+ }
else
{
/* No register. This must be BLX(1). */
static void
do_t_bxj (void)
{
- constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
- if (inst.operands[0].reg == REG_PC)
- as_tsktsk (_("use of r15 in bxj is not really useful"));
+ int Rm;
- inst.instruction |= inst.operands[0].reg << 16;
+ constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+ Rm = inst.operands[0].reg;
+ reject_bad_reg (Rm);
+ inst.instruction |= Rm << 16;
}
static void
do_t_clz (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[1].reg;
+ unsigned Rd;
+ unsigned Rm;
+
+ Rd = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rm << 16;
+ inst.instruction |= Rm;
}
static void
static void
do_t_div (void)
{
- if (!inst.operands[1].present)
- inst.operands[1].reg = inst.operands[0].reg;
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
+ unsigned Rd, Rn, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rn = (inst.operands[1].present
+ ? inst.operands[1].reg : Rd);
+ Rm = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
}
static void
static void
do_t_mla (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
- inst.instruction |= inst.operands[3].reg << 12;
+ unsigned Rd, Rn, Rm, Ra;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+ Rm = inst.operands[2].reg;
+ Ra = inst.operands[3].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+ reject_bad_reg (Ra);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
+ inst.instruction |= Ra << 12;
}
static void
do_t_mlal (void)
{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 8;
- inst.instruction |= inst.operands[2].reg << 16;
- inst.instruction |= inst.operands[3].reg;
+ unsigned RdLo, RdHi, Rn, Rm;
+
+ RdLo = inst.operands[0].reg;
+ RdHi = inst.operands[1].reg;
+ Rn = inst.operands[2].reg;
+ Rm = inst.operands[3].reg;
+
+ reject_bad_reg (RdLo);
+ reject_bad_reg (RdHi);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= RdLo << 12;
+ inst.instruction |= RdHi << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
}
static void
do_t_mov_cmp (void)
{
+ unsigned Rn, Rm;
+
+ Rn = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
if (unified_syntax)
{
int r0off = (inst.instruction == T_MNEM_mov
bfd_boolean narrow;
bfd_boolean low_regs;
- low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
+ low_regs = (Rn <= 7 && Rm <= 7);
opcode = inst.instruction;
if (current_it_mask)
narrow = opcode != T_MNEM_movs;
/* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
if (opcode == T_MNEM_movs && inst.operands[1].isreg
&& !inst.operands[1].shifted
- && inst.operands[0].reg == REG_PC
- && inst.operands[1].reg == REG_LR)
+ && Rn == REG_PC
+ && Rm == REG_LR)
{
inst.instruction = T2_SUBS_PC_LR;
return;
}
+ if (opcode == T_MNEM_cmp)
+ {
+ constraint (Rn == REG_PC, BAD_PC);
+ reject_bad_reg (Rm);
+ }
+ else if (opcode == T_MNEM_mov
+ || opcode == T_MNEM_movs)
+ {
+ if (inst.operands[1].isreg)
+ {
+ if (opcode == T_MNEM_movs)
+ {
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+ }
+ else if ((Rn == REG_SP || Rn == REG_PC)
+ && (Rm == REG_SP || Rm == REG_PC))
+ reject_bad_reg (Rm);
+ }
+ else
+ reject_bad_reg (Rn);
+ }
+
if (!inst.operands[1].isreg)
{
/* Immediate operand. */
if (low_regs && narrow)
{
inst.instruction = THUMB_OP16 (opcode);
- inst.instruction |= inst.operands[0].reg << 8;
+ inst.instruction |= Rn << 8;
if (inst.size_req == 2)
inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
else
{
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
- inst.instruction |= inst.operands[0].reg << r0off;
+ inst.instruction |= Rn << r0off;
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
}
if (!low_regs || inst.operands[1].imm > 7)
narrow = FALSE;
- if (inst.operands[0].reg != inst.operands[1].reg)
+ if (Rn != Rm)
narrow = FALSE;
switch (inst.operands[1].shift_kind)
inst.instruction = opcode;
if (narrow)
{
- inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= Rn;
inst.instruction |= inst.operands[1].imm << 3;
}
else
if (flags)
inst.instruction |= CONDS_BIT;
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= Rn << 8;
+ inst.instruction |= Rm << 16;
inst.instruction |= inst.operands[1].imm;
}
}
if (narrow)
{
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
}
else
{
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << r0off;
+ inst.instruction |= Rn << r0off;
encode_thumb32_shifted_operand (1);
}
}
{
case T_MNEM_mov:
inst.instruction = T_OPCODE_MOV_HR;
- inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
- inst.instruction |= (inst.operands[0].reg & 0x7);
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= (Rn & 0x8) << 4;
+ inst.instruction |= (Rn & 0x7);
+ inst.instruction |= Rm << 3;
break;
case T_MNEM_movs:
/* We know we have low registers at this point.
Generate ADD Rd, Rs, #0. */
inst.instruction = T_OPCODE_ADD_I3;
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
break;
case T_MNEM_cmp:
if (low_regs)
{
inst.instruction = T_OPCODE_CMP_LR;
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
}
else
{
inst.instruction = T_OPCODE_CMP_HR;
- inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
- inst.instruction |= (inst.operands[0].reg & 0x7);
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= (Rn & 0x8) << 4;
+ inst.instruction |= (Rn & 0x7);
+ inst.instruction |= Rm << 3;
}
break;
}
inst.instruction = THUMB_OP16 (inst.instruction);
if (inst.operands[1].isreg)
{
- if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
+ if (Rn < 8 && Rm < 8)
{
/* A move of two lowregs is encoded as ADD Rd, Rs, #0
since a MOV instruction produces unpredictable results. */
else
inst.instruction = T_OPCODE_CMP_LR;
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
}
else
{
}
else
{
- constraint (inst.operands[0].reg > 7,
+ constraint (Rn > 7,
_("only lo regs allowed with immediate"));
- inst.instruction |= inst.operands[0].reg << 8;
+ inst.instruction |= Rn << 8;
inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
}
}
static void
do_t_mov16 (void)
{
+ unsigned Rd;
bfd_vma imm;
bfd_boolean top;
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
}
- inst.instruction |= inst.operands[0].reg << 8;
+ Rd = inst.operands[0].reg;
+ reject_bad_reg (Rd);
+
+ inst.instruction |= Rd << 8;
if (inst.reloc.type == BFD_RELOC_UNUSED)
{
imm = inst.reloc.exp.X_add_number;
static void
do_t_mvn_tst (void)
{
+ unsigned Rn, Rm;
+
+ Rn = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
+ if (inst.instruction == T_MNEM_cmp
+ || inst.instruction == T_MNEM_cmn)
+ constraint (Rn == REG_PC, BAD_PC);
+ else
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
if (unified_syntax)
{
int r0off = (inst.instruction == T_MNEM_mvn
if (inst.size_req == 4
|| inst.instruction > 0xffff
|| inst.operands[1].shifted
- || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
+ || Rn > 7 || Rm > 7)
narrow = FALSE;
else if (inst.instruction == T_MNEM_cmn)
narrow = TRUE;
if (inst.instruction < 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
- inst.instruction |= inst.operands[0].reg << r0off;
+ inst.instruction |= Rn << r0off;
inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
}
else
if (narrow)
{
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
}
else
{
_("shift must be constant"));
if (inst.instruction < 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << r0off;
+ inst.instruction |= Rn << r0off;
encode_thumb32_shifted_operand (1);
}
}
|| inst.instruction == T_MNEM_mvns, BAD_THUMB32);
constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
_("unshifted register required"));
- constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
+ constraint (Rn > 7 || Rm > 7,
BAD_HIREG);
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rn;
+ inst.instruction |= Rm << 3;
}
}
static void
do_t_mrs (void)
{
+ unsigned Rd;
int flags;
if (do_vfp_nsyn_mrs () == SUCCESS)
_("'CPSR' or 'SPSR' expected"));
}
- inst.instruction |= inst.operands[0].reg << 8;
+ Rd = inst.operands[0].reg;
+ reject_bad_reg (Rd);
+
+ inst.instruction |= Rd << 8;
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
}
do_t_msr (void)
{
int flags;
+ unsigned Rn;
if (do_vfp_nsyn_msr () == SUCCESS)
return;
"requested special purpose register"));
flags |= PSR_f;
}
+
+ Rn = inst.operands[1].reg;
+ reject_bad_reg (Rn);
+
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= (flags & ~SPSR_BIT) >> 8;
inst.instruction |= (flags & 0xff);
- inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= Rn << 16;
}
static void
do_t_mul (void)
{
bfd_boolean narrow;
+ unsigned Rd, Rn, Rm;
if (!inst.operands[2].present)
inst.operands[2].reg = inst.operands[0].reg;
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+ Rm = inst.operands[2].reg;
+
if (unified_syntax)
{
if (inst.size_req == 4
- || (inst.operands[0].reg != inst.operands[1].reg
- && inst.operands[0].reg != inst.operands[2].reg)
- || inst.operands[1].reg > 7
- || inst.operands[2].reg > 7)
+ || (Rd != Rn
+ && Rd != Rm)
+ || Rn > 7
+ || Rm > 7)
narrow = FALSE;
else if (inst.instruction == T_MNEM_muls)
narrow = (current_it_mask == 0);
else
{
constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
- constraint (inst.operands[1].reg > 7 || inst.operands[2].reg > 7,
+ constraint (Rn > 7 || Rm > 7,
BAD_HIREG);
narrow = TRUE;
}
{
/* 16-bit MULS/Conditional MUL. */
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg;
+ inst.instruction |= Rd;
- if (inst.operands[0].reg == inst.operands[1].reg)
- inst.instruction |= inst.operands[2].reg << 3;
- else if (inst.operands[0].reg == inst.operands[2].reg)
- inst.instruction |= inst.operands[1].reg << 3;
+ if (Rd == Rn)
+ inst.instruction |= Rm << 3;
+ else if (Rd == Rm)
+ inst.instruction |= Rn << 3;
else
constraint (1, _("dest must overlap one source register"));
}
_("Thumb-2 MUL must not set flags"));
/* 32-bit MUL. */
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg << 0;
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm << 0;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
}
}
static void
do_t_mull (void)
{
- inst.instruction |= inst.operands[0].reg << 12;
- inst.instruction |= inst.operands[1].reg << 8;
- inst.instruction |= inst.operands[2].reg << 16;
- inst.instruction |= inst.operands[3].reg;
+ unsigned RdLo, RdHi, Rn, Rm;
- if (inst.operands[0].reg == inst.operands[1].reg)
+ RdLo = inst.operands[0].reg;
+ RdHi = inst.operands[1].reg;
+ Rn = inst.operands[2].reg;
+ Rm = inst.operands[3].reg;
+
+ reject_bad_reg (RdLo);
+ reject_bad_reg (RdHi);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= RdLo << 12;
+ inst.instruction |= RdHi << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
+
+ if (RdLo == RdHi)
as_tsktsk (_("rdhi and rdlo must be different"));
}
Rd = inst.operands[0].reg;
Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
+ reject_bad_reg (Rd);
+ /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
+ reject_bad_reg (Rn);
+
inst.instruction |= Rd << 8;
inst.instruction |= Rn << 16;
unsigned Rm;
Rm = inst.operands[2].reg;
+ reject_bad_reg (Rm);
constraint (inst.operands[2].shifted
&& inst.operands[2].immisreg,
static void
do_t_pkhbt (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
+ unsigned Rd, Rn, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+ Rm = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
if (inst.operands[3].present)
{
unsigned int val = inst.reloc.exp.X_add_number;
static void
do_t_pld (void)
{
+ if (inst.operands[0].immisreg)
+ reject_bad_reg (inst.operands[0].imm);
+
encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
}
static void
do_t_rbit (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[1].reg;
+ unsigned Rd, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rm << 16;
+ inst.instruction |= Rm;
}
static void
do_t_rev (void)
{
- if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
+ unsigned Rd, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rm);
+
+ if (Rd <= 7 && Rm <= 7
&& inst.size_req != 4)
{
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rd;
+ inst.instruction |= Rm << 3;
}
else if (unified_syntax)
{
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rm << 16;
+ inst.instruction |= Rm;
}
else
inst.error = BAD_HIREG;
Rd = inst.operands[0].reg;
Rm = inst.operands[1].reg;
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rm);
+
inst.instruction |= Rd << 8;
inst.instruction |= Rm;
}
static void
do_t_rsb (void)
{
- int Rd, Rs;
+ unsigned Rd, Rs;
Rd = inst.operands[0].reg;
Rs = (inst.operands[1].present
? inst.operands[1].reg /* Rd, Rs, foo */
: inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rs);
+ if (inst.operands[2].isreg)
+ reject_bad_reg (inst.operands[2].reg);
+
inst.instruction |= Rd << 8;
inst.instruction |= Rs << 16;
if (!inst.operands[2].isreg)
if (inst.size_req == 4)
narrow = FALSE;
+ reject_bad_reg (inst.operands[0].reg);
+ reject_bad_reg (inst.operands[1].reg);
+
if (!narrow)
{
if (inst.operands[2].isreg)
{
+ reject_bad_reg (inst.operands[2].reg);
inst.instruction = THUMB_OP32 (inst.instruction);
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= inst.operands[1].reg << 16;
static void
do_t_simd (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
+ unsigned Rd, Rn, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+ Rm = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
}
static void
static void
do_t_ssat (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+
+ inst.instruction |= Rd << 8;
inst.instruction |= inst.operands[1].imm - 1;
- inst.instruction |= inst.operands[2].reg << 16;
+ inst.instruction |= Rn << 16;
if (inst.operands[3].present)
{
static void
do_t_ssat16 (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+
+ inst.instruction |= Rd << 8;
inst.instruction |= inst.operands[1].imm - 1;
- inst.instruction |= inst.operands[2].reg << 16;
+ inst.instruction |= Rn << 16;
}
static void
static void
do_t_sxtah (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg << 16;
- inst.instruction |= inst.operands[2].reg;
+ unsigned Rd, Rn, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[1].reg;
+ Rm = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+ reject_bad_reg (Rm);
+
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rn << 16;
+ inst.instruction |= Rm;
inst.instruction |= inst.operands[3].imm << 4;
}
static void
do_t_sxth (void)
{
+ unsigned Rd, Rm;
+
+ Rd = inst.operands[0].reg;
+ Rm = inst.operands[1].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rm);
+
if (inst.instruction <= 0xffff && inst.size_req != 4
- && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
+ && Rd <= 7 && Rm <= 7
&& (!inst.operands[2].present || inst.operands[2].imm == 0))
{
inst.instruction = THUMB_OP16 (inst.instruction);
- inst.instruction |= inst.operands[0].reg;
- inst.instruction |= inst.operands[1].reg << 3;
+ inst.instruction |= Rd;
+ inst.instruction |= Rm << 3;
}
else if (unified_syntax)
{
if (inst.instruction <= 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
- inst.instruction |= inst.operands[0].reg << 8;
- inst.instruction |= inst.operands[1].reg;
+ inst.instruction |= Rd << 8;
+ inst.instruction |= Rm;
inst.instruction |= inst.operands[2].imm << 4;
}
else
static void
do_t_tb (void)
{
+ unsigned Rn, Rm;
int half;
half = (inst.instruction & 0x10) != 0;
constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
constraint (inst.operands[0].immisreg,
_("instruction requires register index"));
- constraint (inst.operands[0].imm == 15,
- _("PC is not a valid index register"));
+
+ Rn = inst.operands[0].reg;
+ Rm = inst.operands[0].imm;
+
+ constraint (Rn == REG_SP, BAD_SP);
+ reject_bad_reg (Rm);
+
constraint (!half && inst.operands[0].shifted,
_("instruction does not allow shifted index"));
- inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
+ inst.instruction |= (Rn << 16) | Rm;
}
static void
do_t_usat (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+
+ inst.instruction |= Rd << 8;
inst.instruction |= inst.operands[1].imm;
- inst.instruction |= inst.operands[2].reg << 16;
+ inst.instruction |= Rn << 16;
if (inst.operands[3].present)
{
static void
do_t_usat16 (void)
{
- inst.instruction |= inst.operands[0].reg << 8;
+ unsigned Rd, Rn;
+
+ Rd = inst.operands[0].reg;
+ Rn = inst.operands[2].reg;
+
+ reject_bad_reg (Rd);
+ reject_bad_reg (Rn);
+
+ inst.instruction |= Rd << 8;
inst.instruction |= inst.operands[1].imm;
- inst.instruction |= inst.operands[2].reg << 16;
+ inst.instruction |= Rn << 16;
}
/* Neon instruction encoder helpers. */
{
inst.operands[1] = inst.operands[0];
memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
- inst.operands[0].reg = 13;
+ inst.operands[0].reg = REG_SP;
inst.operands[0].isreg = 1;
inst.operands[0].writeback = 1;
inst.operands[0].present = 1;
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `addw r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r13,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r13,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `adr.w r13,test'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `adr.w r15,test'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `and r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `and r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `and r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `and r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bfc r13,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bfc r15,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r13,r0,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r15,r0,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r0,r13,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r0,r15,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `blx r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `bxj r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `bxj r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r0,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn r15,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `cmn.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r0,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp r15,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `cmp.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mcr p0,#1,r13,cr0,cr0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mcr p0,#1,r15,cr0,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r13,r0,cr0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r15,r0,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r0,r13,cr0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r0,r15,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,r13'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r15,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r13,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `movt r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `movt r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mrc p0,#1,r13,cr0,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r13,r0,cr0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r15,r0,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r0,r13,cr0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r0,r15,cr0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mrs r13,cpsr'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mrs r15,cpsr'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `msr cpsr,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `msr cpsr,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `pld \[r0,r13\]'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `pld \[r0,r15\]'
+[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pld \[r15,r0\]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `pli \[r0,r13\]'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `pli \[r0,r15\]'
+[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pli \[r15,r0\]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r0,r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rfedb r15'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rfeia r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r13,r0,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r15,r0,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r0,r13,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r0,r15,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r13,#1,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r15,#1,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r0,#1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r0,#1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r13,#1,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r15,#1,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r0,#1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r0,#1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,#1'
+[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `subw r13,r0,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r0,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r1,r15'
+[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r13,#1'
+[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `subs.w r15,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r13,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r13,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r13,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r13,r0]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r0,r13]'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `tbb \[r0,r15]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r13,r0]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r0,r13]'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `tbh \[r0,r15]'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tst r13,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `tst r15,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r13,r0,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r15,r0,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r0,r13,#1,#1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r0,r15,#1,#1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r13,r0,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r15,r0,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r13,r0,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r15,r0,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r13,#1,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r15,#1,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r0,#1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r0,#1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r13,#1,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r15,#1,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r0,#1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r0,#1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r13,r0,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r15,r0,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r13,r1'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r15,r1'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r1,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r1,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r0,r15'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r13,r0'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r15,r0'
+[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r0,r13'
+[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r0,r15'
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