+2007-09-23 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * config/mips/mips.h (ISA_HAS_DSP, ISA_HAS_DSPR2): New macros.
+ * config/mips/mips.c (mips_set_mips16_mode): Don't clear the DSP
+ flags for MIPS16.
+ (override_options): Check TARGET_HARD_FLOAT_ABI instead of
+ TARGET_HARD_FLOAT when testing whether -mpaired-single is
+ supported.
+ (mips_conditional_register_usage): Check ISA_HAS_DSP instead of
+ TARGET_DSP.
+ * config/mips/constraints.md (ka): Check ISA_HAS_DSPR2 instead of
+ TARGET_DSPR2.
+ * config/mips/mips.md (ANYF): Require TARGET_HARD_FLOAT for V2SF.
+ (mulv2sf3, movv2sf, movv2sf_hardfloat_64bit): Require
+ TARGET_HARD_FLOAT.
+ (<u>mulsidi3_32bit_internal, <u>msubsidi4, <u>maddsidi4): Check
+ ISA_HAS_DSPR2 instead of TARGET_HAS_DSPR2.
+ * config/mips/mips-dsp.md: Use ISA_HAS_DSP instead of TARGET_HAS_DSP
+ throughout.
+ * config/mips/mips-dspr2.md: Likewise ISA_HAS_DSPR2 and
+ TARGET_HAS_DSPR2.
+ * config/mips/mips-fixed.md: Use ISA_HAS_DSP and ISA_HAS_DSPR2
+ instead of TARGET_HAS_DSP and TARGET_HAS_DSPR2.
+ * config/mips/mips-ps-3d.md: Add TARGET_HARD_FLOAT to V2SF patterns.
+
2007-09-22 Jason Merrill <jason@redhat.com>
PR c++/19407
;; Registers that can be used as the target of multiply-accumulate
;; instructions. The core MIPS32 ISA provides a hi/lo madd,
;; but the DSPr2 version allows any accumulator target.
-(define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS")
+(define_register_constraint "ka" "ISA_HAS_DSPR2 ? ACC_REGS : MD_REGS")
(define_constraint "kf"
"@internal"
(CCDSP_EF_REGNUM 187)])
;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
-(define_mode_iterator DSP [(SI "TARGET_DSP")
- (V2HI "TARGET_DSP")
- (V4QI "TARGET_DSP")])
+(define_mode_iterator DSP [(SI "ISA_HAS_DSP")
+ (V2HI "ISA_HAS_DSP")
+ (V4QI "ISA_HAS_DSP")])
;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
-(define_mode_iterator DSPV [(V2HI "TARGET_DSP")
- (V4QI "TARGET_DSP")])
+(define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
+ (V4QI "ISA_HAS_DSP")])
;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
-(define_mode_iterator DSPQ [(SI "TARGET_DSP")
- (V2HI "TARGET_DSP")])
+(define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
+ (V2HI "ISA_HAS_DSP")])
;; DSP instructions use q for fixed-point data, and u for integer in the infix.
(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
(match_operand:DSPV 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_SUBQ_S))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_ADDSC))
(set (reg:CCDSP CCDSP_CA_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"addsc\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_ADDWC))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"addwc\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")]
UNSPEC_MODSUB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"modsub\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_RADDU_W_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"raddu.w.qb\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_ABSQ_S))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"absq_s.<DSPQ:dspfmt2>\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d")]
UNSPEC_PRECRQ_QB_PH))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precrq.qb.ph\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")]
UNSPEC_PRECRQ_PH_W))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precrq.ph.w\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
UNSPEC_PRECRQ_RS_PH_W))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precrq_rs.ph.w\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)]
UNSPEC_PRECRQU_S_QB_PH))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precrqu_s.qb.ph\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
UNSPEC_PRECEQ_W_PHL))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceq.w.phl\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
UNSPEC_PRECEQ_W_PHR))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceq.w.phr\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEQU_PH_QBL))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precequ.ph.qbl\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEQU_PH_QBR))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precequ.ph.qbr\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEQU_PH_QBLA))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precequ.ph.qbla\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEQU_PH_QBRA))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"precequ.ph.qbra\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEU_PH_QBL))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceu.ph.qbl\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEU_PH_QBR))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceu.ph.qbr\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEU_PH_QBLA))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceu.ph.qbla\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V2HI 0 "register_operand" "=d")
(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
UNSPEC_PRECEU_PH_QBRA))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"preceu.ph.qbra\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_SHLL))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
UNSPEC_SHLL_S))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRL_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRA_PH))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRA_R))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"muleu_s.ph.qbl\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"muleu_s.ph.qbr\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"mulq_rs.ph\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"muleq_s.w.phl\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"muleq_s.w.phr\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(match_operand:V4QI 2 "register_operand" "d")
(match_operand:V4QI 3 "register_operand" "d")]
UNSPEC_DPAU_H_QBL))]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpau.h.qbl\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(match_operand:V4QI 2 "register_operand" "d")
(match_operand:V4QI 3 "register_operand" "d")]
UNSPEC_DPAU_H_QBR))]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpau.h.qbr\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(match_operand:V4QI 2 "register_operand" "d")
(match_operand:V4QI 3 "register_operand" "d")]
UNSPEC_DPSU_H_QBL))]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpsu.h.qbl\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(match_operand:V4QI 2 "register_operand" "d")
(match_operand:V4QI 3 "register_operand" "d")]
UNSPEC_DPSU_H_QBR))]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpsu.h.qbr\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQ_S_W_PH))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQ_S_W_PH))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_MULSAQ_S_W_PH))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"mulsaq_s.w.ph\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQ_SA_L_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_sa.l.w\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQ_SA_L_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_sa.l.w\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_MAQ_S_W_PHL))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"maq_s.w.phl\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_MAQ_S_W_PHR))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"maq_s.w.phr\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_MAQ_SA_W_PHL))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"maq_sa.w.phl\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_MAQ_SA_W_PHR))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"maq_sa.w.phr\t%q0,%2,%3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec:SI [(match_operand:SI 1 "register_operand" "d")]
UNSPEC_BITREV))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"bitrev\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(reg:CCDSP CCDSP_SC_REGNUM)
(reg:CCDSP CCDSP_PO_REGNUM)]
UNSPEC_INSV))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"insv\t%0,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
[(set (match_operand:V4QI 0 "register_operand" "=d,d")
(unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
UNSPEC_REPL_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
{
if (which_alternative == 0)
{
[(set (match_operand:V2HI 0 "register_operand" "=d,d")
(unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
UNSPEC_REPL_PH))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"@
repl.ph\t%0,%1
replv.ph\t%0,%1"
(match_operand:DSPV 1 "register_operand" "d")
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMP_EQ))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:DSPV 1 "register_operand" "d")
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMP_LT))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:DSPV 1 "register_operand" "d")
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMP_LE))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
(match_operand:V4QI 2 "register_operand" "d")]
UNSPEC_CMPGU_EQ_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmpgu.eq.qb\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
(match_operand:V4QI 2 "register_operand" "d")]
UNSPEC_CMPGU_LT_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmpgu.lt.qb\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
(match_operand:V4QI 2 "register_operand" "d")]
UNSPEC_CMPGU_LE_QB))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"cmpgu.le.qb\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:DSPV 2 "register_operand" "d")
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_PICK))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"pick.<DSPV:dspfmt2>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
(match_operand:V2HI 2 "register_operand" "d")]
UNSPEC_PACKRL_PH))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"packrl.ph\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_EXTR_W))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
UNSPEC_EXTR_R_W))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
UNSPEC_EXTR_RS_W))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
UNSPEC_EXTR_S_H))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
UNSPEC_EXTP))
(set (reg:CCDSP CCDSP_EF_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
(set (reg:CCDSP CCDSP_EF_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
(unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHILO))]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
{
if (which_alternative == 0)
{
(set (reg:CCDSP CCDSP_PO_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"mthlip\t%2,%q0"
[(set_attr "type" "mfhilo")
(set_attr "mode" "SI")])
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
(set (reg:CCDSP CCDSP_EF_REGNUM)
(unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"wrdsp\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(reg:CCDSP CCDSP_CC_REGNUM)
(reg:CCDSP CCDSP_EF_REGNUM)]
UNSPEC_RDDSP))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"rddsp\t%0,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
"register_operand" "d")
(match_operand:SI 2
"register_operand" "d")))))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"lbux\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
"register_operand" "d")
(match_operand:SI 2
"register_operand" "d")))))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"lhx\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
[(set (match_operand:SI 0 "register_operand" "=d")
(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"lwx\t%0,%2(%1)"
[(set_attr "type" "load")
(set_attr "mode" "SI")
(match_operand:SI 0 "immediate_operand" "I"))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"%*bposge%0\t%1%/"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
UNSPEC_ABSQ_S_QB))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"absq_s.qb\t%0,%z1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addu.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_ADDU_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
UNSPEC_ADDUH_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"adduh.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
UNSPEC_ADDUH_R_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"adduh_r.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:SI 2 "reg_or_0_operand" "dJ")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_APPEND))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
(match_operand:SI 2 "reg_or_0_operand" "dJ")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_BALIGN))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_EQ_QB))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"cmpgdu.eq.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_LT_QB))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"cmpgdu.lt.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:CCDSP [(match_dup 1) (match_dup 2)
(reg:CCDSP CCDSP_CC_REGNUM)]
UNSPEC_CMPGDU_LE_QB))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"cmpgdu.le.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
UNSPEC_DPA_W_PH))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
UNSPEC_DPS_W_PH))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dps.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
(any_extend:DI (match_operand:SI 3 "register_operand")))
(match_operand:DI 1 "register_operand")))]
- "TARGET_DSPR2 && !TARGET_64BIT")
+ "ISA_HAS_DSPR2 && !TARGET_64BIT")
(define_expand "mips_msub<u>"
[(set (match_operand:DI 0 "register_operand")
(match_operand:DI 1 "register_operand")
(mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
(any_extend:DI (match_operand:SI 3 "register_operand")))))]
- "TARGET_DSPR2 && !TARGET_64BIT")
+ "ISA_HAS_DSPR2 && !TARGET_64BIT")
(define_insn "mulv2hi3"
[(parallel
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"mul.ph\t%0,%1,%2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"mul_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"mulq_rs.w\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"mulq_s.ph\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
(clobber (match_scratch:DI 3 "=x"))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"mulq_s.w\t%0,%z1,%z2"
[(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
UNSPEC_MULSA_W_PH))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"mulsa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(mult:DI
(sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"mult\t%q0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(mult:DI
(zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
(zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"multu\t%q0,%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_PRECR_QB_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"precr.qb.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:SI 2 "reg_or_0_operand" "dJ")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_PRECR_SRA_PH_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
(match_operand:SI 2 "reg_or_0_operand" "dJ")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_PRECR_SRA_R_PH_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
(match_operand:SI 2 "reg_or_0_operand" "dJ")
(match_operand:SI 3 "const_int_operand" "n")]
UNSPEC_PREPEND))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRA_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (which_alternative == 0)
{
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRA_R_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (which_alternative == 0)
{
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
(match_operand:SI 2 "arith_operand" "I,d")]
UNSPEC_SHRL_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
{
if (which_alternative == 0)
{
UNSPEC_SUBU_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subu.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
UNSPEC_SUBU_S_PH))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subu_s.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBUH_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subuh.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
(match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBUH_R_QB))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subuh_r.qb\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_ADDQH_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addqh.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_ADDQH_R_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addqh_r.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_ADDQH_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addqh.w\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_ADDQH_R_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"addqh_r.w\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBQH_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subqh.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
UNSPEC_SUBQH_R_PH))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subqh_r.ph\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_SUBQH_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subqh.w\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
(match_operand:SI 2 "reg_or_0_operand" "dJ")]
UNSPEC_SUBQH_R_W))]
- "TARGET_DSPR2"
+ "ISA_HAS_DSPR2"
"subqh_r.w\t%0,%z1,%z2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
UNSPEC_DPAX_W_PH))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpax.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(match_operand:V2HI 2 "reg_or_0_operand" "dYG")
(match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
UNSPEC_DPSX_W_PH))]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsx.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQX_S_W_PH))])]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQX_SA_W_PH))])]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpaqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQX_S_W_PH))])]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_s.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQX_SA_W_PH))])]
- "TARGET_DSPR2 && !TARGET_64BIT"
+ "ISA_HAS_DSPR2 && !TARGET_64BIT"
"dpsqx_sa.w.ph\t%q0,%z2,%z3"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(V2HQ "ph") (V2HA "ph")])
;; For unsigned add/sub with saturation
-(define_mode_iterator UADDSUB [(UQQ "TARGET_DSP") (UHQ "TARGET_DSPR2")
- (UHA "TARGET_DSPR2") (V4UQQ "TARGET_DSP")
- (V2UHQ "TARGET_DSPR2") (V2UHA "TARGET_DSPR2")])
+(define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
+ (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
+ (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
(define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
(V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])
;; For signed multiplication with saturation
-(define_mode_iterator MULQ [(V2HQ "TARGET_DSP") (HQ "TARGET_DSP")
- (SQ "TARGET_DSPR2")])
+(define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
+ (SQ "ISA_HAS_DSPR2")])
(define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])
(define_insn "add<mode>3"
(match_operand:ADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"addq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")])
(match_operand:ADDSUB 2 "register_operand" "d")))
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
- "TARGET_DSP"
+ "ISA_HAS_DSP"
"subq_s.<addsubfmt>\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<IMODE>")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPAQ_SA_L_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpaq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(set (reg:CCDSP CCDSP_OU_REGNUM)
(unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
UNSPEC_DPSQ_SA_L_W))])]
- "TARGET_DSP && !TARGET_64BIT"
+ "ISA_HAS_DSP && !TARGET_64BIT"
"dpsq_sa.l.w\t%q0,%1,%2"
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
(const_int 0)])
(match_operand:V2SF 2 "register_operand" "f,0")
(match_operand:V2SF 3 "register_operand" "0,f")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"@
mov%T4.ps\t%0,%2,%1
mov%t4.ps\t%0,%3,%1"
(match_operand:V2SF 2 "register_operand" "0,f")
(match_operand:CCV2 3 "register_operand" "z,z")]
UNSPEC_MOVE_TF_PS))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"@
movt.ps\t%0,%1,%3
movf.ps\t%0,%2,%3"
(if_then_else:V2SF (match_dup 5)
(match_operand:V2SF 2 "register_operand")
(match_operand:V2SF 3 "register_operand")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
/* We can only support MOVN.PS and MOVZ.PS.
NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
(match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")
(const_int 2)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"pul.ps\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "SF")])
(parallel [(const_int 1)
(const_int 0)]))
(const_int 2)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"puu.ps\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "SF")])
(const_int 0)]))
(match_operand:V2SF 2 "register_operand" "f")
(const_int 2)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"pll.ps\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "SF")])
(parallel [(const_int 1)
(const_int 0)]))
(const_int 2)))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"plu.ps\t%0,%1,%2"
[(set_attr "type" "fmove")
(set_attr "mode" "SF")])
(define_expand "vec_initv2sf"
[(match_operand:V2SF 0 "register_operand")
(match_operand:V2SF 1 "")]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
(vec_concat:V2SF
(match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
if (BYTES_BIG_ENDIAN)
return "cvt.ps.s\t%0,%1,%2";
(vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
(parallel
[(match_operand 2 "const_0_or_1_operand" "")])))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
return "cvt.s.pu\t%0,%1";
[(match_operand:V2SF 0 "register_operand")
(match_operand:SF 1 "register_operand")
(match_operand 2 "const_0_or_1_operand")]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
rtx temp;
[(match_operand:V2SF 0 "register_operand")
(match_operand:SF 1 "register_operand")
(match_operand:SF 2 "register_operand")]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
if (BYTES_BIG_ENDIAN)
emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
[(set (match_operand:SF 0 "register_operand")
(vec_select:SF (match_operand:V2SF 1 "register_operand")
(parallel [(match_dup 2)])))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{ operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
[(set (match_operand:SF 0 "register_operand")
(vec_select:SF (match_operand:V2SF 1 "register_operand")
(parallel [(match_dup 2)])))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{ operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
; alnv.ps - Floating Point Align Variable
(match_operand:V2SF 2 "register_operand" "f")
(match_operand:SI 3 "register_operand" "d")]
UNSPEC_ALNV_PS))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"alnv.ps\t%0,%1,%2,%3"
[(set_attr "type" "fmove")
(set_attr "mode" "SF")])
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")]
UNSPEC_ADDR_PS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"addr.ps\t%0,%1,%2"
[(set_attr "type" "fadd")
(set_attr "mode" "SF")])
[(set (match_operand:V2SF 0 "register_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
UNSPEC_CVT_PW_PS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"cvt.pw.ps\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
[(set (match_operand:V2SF 0 "register_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
UNSPEC_CVT_PS_PW))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"cvt.ps.pw\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")]
UNSPEC_MULR_PS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"mulr.ps\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
[(set (match_operand:V2SF 0 "register_operand")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
UNSPEC_ABS_PS))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
/* If we can ignore NaNs, this operation is equivalent to the
rtl ABS code. */
[(set (match_operand:V2SF 0 "register_operand" "=f")
(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
UNSPEC_ABS_PS))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"abs.ps\t%0,%1"
[(set_attr "type" "fabs")
(set_attr "mode" "SF")])
(match_operand:SCALARF 2 "register_operand" "f")
(match_operand 3 "const_int_operand" "")]
UNSPEC_CABS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"cabs.%Y3.<fmt>\t%0,%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(match_operand:V2SF 4 "register_operand" "f")
(match_operand 5 "const_int_operand" "")]
UNSPEC_C))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"#"
"&& reload_completed"
[(set (match_dup 6)
(match_operand:V2SF 4 "register_operand" "f")
(match_operand 5 "const_int_operand" "")]
UNSPEC_CABS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"#"
"&& reload_completed"
[(set (match_dup 6)
(match_operand:V2SF 2 "register_operand" "f")
(match_operand 3 "const_int_operand" "")]
UNSPEC_C))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"c.%Y3.ps\t%0,%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(match_operand:V2SF 2 "register_operand" "f")
(match_operand 3 "const_int_operand" "")]
UNSPEC_CABS))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"cabs.%Y3.ps\t%0,%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
[(fcond (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))]
UNSPEC_SCC))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"c.<fcond>.ps\t%0,%1,%2"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
[(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f"))]
UNSPEC_SCC))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"c.<swapped_fcond>.ps\t%0,%2,%1"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"%*bc1any4t\t%0,%1%/"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"%*bc1any4f\t%0,%1%/"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"%*bc1any2t\t%0,%1%/"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
(const_int -1))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"%*bc1any2f\t%0,%1%/"
[(set_attr "type" "branch")
(set_attr "mode" "none")])
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RSQRT1))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"rsqrt1.<fmt>\t%0,%1"
[(set_attr "type" "frsqrt1")
(set_attr "mode" "<UNITMODE>")])
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")]
UNSPEC_RSQRT2))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"rsqrt2.<fmt>\t%0,%1,%2"
[(set_attr "type" "frsqrt2")
(set_attr "mode" "<UNITMODE>")])
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RECIP1))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"recip1.<fmt>\t%0,%1"
[(set_attr "type" "frdiv1")
(set_attr "mode" "<UNITMODE>")])
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f")]
UNSPEC_RECIP2))]
- "TARGET_MIPS3D"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"recip2.<fmt>\t%0,%1,%2"
[(set_attr "type" "frdiv2")
(set_attr "mode" "<UNITMODE>")])
(match_operand:V2SF 5 "register_operand")])
(match_operand:V2SF 1 "register_operand")
(match_operand:V2SF 2 "register_operand")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
GET_CODE (operands[3]), operands[4], operands[5]);
[(set (match_operand:V2SF 0 "register_operand")
(smin:V2SF (match_operand:V2SF 1 "register_operand")
(match_operand:V2SF 2 "register_operand")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
LE, operands[1], operands[2]);
[(set (match_operand:V2SF 0 "register_operand")
(smax:V2SF (match_operand:V2SF 1 "register_operand")
(match_operand:V2SF 2 "register_operand")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
LE, operands[2], operands[1]);
we use a %gprel() operator. */
target_flags &= ~MASK_EXPLICIT_RELOCS;
- /* Silently disable DSP extensions. */
- target_flags &= ~MASK_DSP;
- target_flags &= ~MASK_DSPR2;
-
/* Experiments suggest we get the best overall results from using
the range of an unextended lw or sw. Code that makes heavy use
of byte or short accesses can do better with ranges of 0...31
target_flags |= MASK_PAIRED_SINGLE_FLOAT;
/* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
- and TARGET_HARD_FLOAT are both true. */
- if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
+ and TARGET_HARD_FLOAT_ABI are both true. */
+ if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
/* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
void
mips_conditional_register_usage (void)
{
- if (!TARGET_DSP)
+ if (!ISA_HAS_DSP)
{
int regno;
/* ISA has lwxs instruction (load w/scaled index address. */
#define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
+/* The DSP ASE is available. */
+#define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
+
+/* Revision 2 of the DSP ASE is available. */
+#define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
+
/* True if the result of a load is not available to the next instruction.
A nop will then be needed between instructions like "lw $4,..."
and "addiu $4,$4,1". */
;; floating-point mode is allowed.
(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
- (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+ (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
;; Like ANYF, but only applies to scalar modes.
(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
[(set (match_operand:V2SF 0 "register_operand" "=f")
(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
(match_operand:V2SF 2 "register_operand" "f")))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
"mul.ps\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
- "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
+ "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
"mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
- "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
+ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
{
- if (TARGET_DSPR2)
+ if (ISA_HAS_DSPR2)
return "msub<u>\t%q0,%1,%2";
else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
return "msub<u>\t%1,%2";
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
- "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
+ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad<u>\t%1,%2";
- else if (TARGET_DSPR2)
+ else if (ISA_HAS_DSPR2)
return "madd<u>\t%q0,%1,%2";
else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
return "madd<u>\t%1,%2";
(define_expand "movv2sf"
[(set (match_operand:V2SF 0)
(match_operand:V2SF 1))]
- "TARGET_PAIRED_SINGLE_FLOAT"
+ "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
{
if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
DONE;
(define_insn "movv2sf_hardfloat_64bit"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
(match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
- "TARGET_PAIRED_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT
&& TARGET_64BIT
+ && TARGET_PAIRED_SINGLE_FLOAT
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
+2007-09-23 Richard Sandiford <rsandifo@nildram.co.uk>
+
+ * lib/target-supports.exp (check_effective_target_nomips16): New
+ procedure.
+ * lib/fortran-torture.exp: Check nomips16 as well as mpaired_single
+ for mipsisa64*-*-*.
+ * gcc.dg/vect/vect.exp: Likewise.
+ * g++.dg/vect/vect.exp: Likewise.
+ * gcc.target/mips/mips.exp (setup_mips_tests): Don't set mips_mips16.
+ (dg-mips-options): Don't skip -march* and -mips* tests for -mips16.
+ * gcc.target/mips/branch-cost-1.c (foo): Add NOMIPS16.
+ * gcc.target/mips/branch-cost-2.c (foo): Likewise.
+ * gcc.target/mips/clear-cache-1.c (f): Likewise.
+ * gcc.target/mips/dpaq_sa_l_w.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/dpsq_sa_l_w.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/fix-vr4130-1.c (foo): Likewise.
+ * gcc.target/mips/fix-vr4130-2.c (foo): Likewise.
+ * gcc.target/mips/fix-vr4130-3.c (foo): Likewise.
+ * gcc.target/mips/fix-vr4130-4.c (foo): Likewise.
+ * gcc.target/mips/fixed-scalar-type.c (test1, test2, test3, test4)
+ (test5, test6, test7, test8, test9, test10, test11, test12, test13)
+ (test14, test15, test16, test17, test18): Likewise.
+ * gcc.target/mips/fixed-vector-type.c (test1, test2, test3, test4)
+ (test5, test6, test7, test8, test9, test10, test11, test12, test13)
+ (test14, test15, test16, test17, test18, test19, test20, test21)
+ (test22): Likewise.
+ * gcc.target/mips/madd-1.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/madd-2.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/madd-4.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/maddu-1.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/maddu-2.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/maddu-4.c (f1, f2, f3): Likewise.
+ * gcc.target/mips/mips-3d-1.c (main): Likewise.
+ * gcc.target/mips/mips-3d-2.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-3d-3.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31, test32, test33, test34, test35, test36)
+ (test37, test38, test39, test40, test41, test42, test43, test44)
+ (test45, test46, test47, test48, test49, test50, test51, test52)
+ (test53, test54, test55, test56, test57, test58, test59, test60)
+ (test61, test62, test63): Likewise.
+ * gcc.target/mips/mips-3d-4.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-3d-5.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-3d-6.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15): Likewise.
+ * gcc.target/mips/mips-3d-7.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15): Likewise.
+ * gcc.target/mips/mips-3d-8.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-3d-9.c (matrix_multiply2, matrix_multiply3)
+ (matrix_multiply4: Likewise.
+ * gcc.target/mips/mips-ps-1.c (main): Likewise.
+ * gcc.target/mips/mips-ps-2.c (main): Likewise.
+ * gcc.target/mips/mips-ps-3.c (main): Likewise.
+ * gcc.target/mips/mips-ps-4.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-ps-5.c (main, test0, test1, test2, test3)
+ (test4, test5, test6, test7, test8, test9, test10, test11, test12)
+ (test13, test14, test15, test16, test17, test18, test19, test20)
+ (test21, test22, test23, test24, test25, test26, test27, test28)
+ (test29, test30, test31): Likewise.
+ * gcc.target/mips/mips-ps-5.c (main): Likewise.
+ * gcc.target/mips/mips-ps-6.c (main): Likewise.
+ * gcc.target/mips/mips-ps-type.c (init, move, load, store, add, sub)
+ (neg, mul, madd, msub, nmadd, nmsub, cond_move1, cond_move2): Likewise.
+ * gcc.target/mips/mips32-dsp-type.c (add_v2hi,add_v4qi, sub_v2hi)
+ (sub_v4qi): Likewise.
+ * gcc.target/mips/mips32-dsp.c (test_MIPS_DSP, add_v2q15, add_v4i8)
+ (sub_v2q15, sub_v4i8, test_MIPS_DSP): Likewise.
+ * gcc.target/mips/movcc-1.c (sub1, sub2): Likewise.
+ * gcc.target/mips/movcc-2.c (sub4, sub5): Likewise.
+ * gcc.target/mips/movcc-3.c (sub3, sub6, sub7, sub8, sub9, suba)
+ (subb, subc): Likewise.
+ * gcc.target/mips/msub-1.c (f1, f2): Likewise.
+ * gcc.target/mips/msub-2.c (f1, f2): Likewise.
+ * gcc.target/mips/msub-4.c (f1, f2): Likewise.
+ * gcc.target/mips/msubu-1.c (f1, f2): Likewise.
+ * gcc.target/mips/msubu-2.c (f1, f2): Likewise.
+ * gcc.target/mips/msubu-4.c (f1, f2): Likewise.
+ * gcc.target/mips/nmadd-1.c (sub1, sub2, sub3, sub4): Likewise.
+ * gcc.target/mips/nmadd-2.c (sub1, sub2, sub3, sub4): Likewise.
+ * gcc.target/mips/rsqrt-1.c (foo, bar): Likewise.
+ * gcc.target/mips/rsqrt-2.c (foo, bar): Likewise.
+ * gcc.target/mips/sb1-1.c (divide, recip, squareroot, rsqrt): Likewise.
+ * gcc.target/mips/vr-mult-1.c (f1, f2): Likewise.
+ * gcc.target/mips/vr-mult-2.c (f1, f2): Likewise.
+
2007-09-22 Richard Sandiford <rsandifo@nildram.co.uk>
* lib/target-supports.exp (add_options_for_mips16_attribute)
lappend DEFAULT_VECTCFLAGS "-msse2"
set dg-do-what-default run
} elseif { [istarget "mipsisa64*-*-*"]
- && [check_effective_target_mpaired_single] } {
+ && [check_effective_target_mpaired_single]
+ && [check_effective_target_nomips16] } {
lappend DEFAULT_VECTCFLAGS "-mpaired-single"
set dg-do-what-default run
} elseif [istarget "sparc*-*-*"] {
lappend DEFAULT_VECTCFLAGS "-msse2"
set dg-do-what-default run
} elseif { [istarget "mipsisa64*-*-*"]
- && [check_effective_target_mpaired_single] } {
+ && [check_effective_target_mpaired_single]
+ && [check_effective_target_nomips16] } {
lappend DEFAULT_VECTCFLAGS "-mpaired-single"
set dg-do-what-default run
} elseif [istarget "sparc*-*-*"] {
/* { dg-mips-options "-mbranch-cost=1 -mips64 -O2" } */
-int
+NOMIPS16 int
foo (int x, int y, int z, int k)
{
return x == k ? x + y : z - x;
/* { dg-mips-options "-mbranch-cost=10 -mips64 -O2" } */
-int
+NOMIPS16 int
foo (int x, int y, int z, int k)
{
return x == k ? x + y : z - x;
/* { dg-final { scan-assembler "jr.hb" } } */
/* { dg-final { scan-assembler-not "_flush_cache" } } */
-void f()
+NOMIPS16 void f()
{
int size = 40;
char *memory = __builtin_alloca(size);
/* { dg-mips-options "-O2 -mips32r2 -mdsp" } */
/* { dg-final { scan-assembler-times "\tdpaq_sa.l.w\t\\\$ac" 3 } } */
-_Sat long long _Fract
+NOMIPS16 _Sat long long _Fract
f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
{
return (_Sat long long _Fract) x * y + z;
}
-_Sat long long _Fract
+NOMIPS16 _Sat long long _Fract
f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
{
return z + (_Sat long long _Fract) y * x;
}
-_Sat long long _Fract
+NOMIPS16 _Sat long long _Fract
f3 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
{
_Sat long long _Fract t = (_Sat long long _Fract) x * y;
/* { dg-mips-options "-O2 -mips32r2 -mdsp" } */
/* { dg-final { scan-assembler-times "\tdpsq_sa.l.w\t\\\$ac" 2 } } */
-_Sat long long _Fract
+NOMIPS16 _Sat long long _Fract
f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
{
return z - (_Sat long long _Fract) x * y;
}
-_Sat long long _Fract
+NOMIPS16 _Sat long long _Fract
f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
{
_Sat long long _Fract t = (_Sat long long _Fract) x * y;
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */
-int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; }
+NOMIPS16 int foo (void) { int r; asm ("# foo" : "=h" (r)); return r; }
/* { dg-final { scan-assembler "\tmacchi\t" } } */
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mfix-vr4130" } */
-int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; }
+NOMIPS16 int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; }
/* { dg-final { scan-assembler "\tmacc\t" } } */
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
-long long foo (void) { long long r; asm ("# foo" : "=h" (r)); return r; }
+NOMIPS16 long long
+foo (void)
+{
+ long long r;
+ asm ("# foo" : "=h" (r));
+ return r;
+}
/* { dg-final { scan-assembler "\tdmacchi\t" } } */
/* { dg-do compile } */
/* { dg-mips-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
-long long foo (void) { long long r; asm ("# foo" : "=l" (r)); return r; }
+NOMIPS16 long long
+foo (void)
+{
+ long long r;
+ asm ("# foo" : "=l" (r));
+ return r;
+}
/* { dg-final { scan-assembler "\tdmacc\t" } } */
}
unsigned short _Fract non_sat_test14 (unsigned short _Fract a,
- unsigned short _Fract b)
+ unsigned short _Fract b)
{
return a - b;
}
}
unsigned long _Fract non_sat_test16 (unsigned long _Fract a,
- unsigned long _Fract b)
+ unsigned long _Fract b)
{
return a - b;
}
}
unsigned short _Accum non_sat_test19 (unsigned short _Accum a,
- unsigned short _Accum b)
+ unsigned short _Accum b)
{
return a - b;
}
return a - b;
}
-_Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a,
- _Sat unsigned short _Fract b)
+NOMIPS16 _Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a,
+ _Sat unsigned short _Fract b)
{
return a + b;
}
-_Sat unsigned _Fract test2 (_Sat unsigned _Fract a, _Sat unsigned _Fract b)
+NOMIPS16 _Sat unsigned _Fract test2 (_Sat unsigned _Fract a,
+ _Sat unsigned _Fract b)
{
return a + b;
}
-_Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a,
- _Sat unsigned short _Accum b)
+NOMIPS16 _Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a,
+ _Sat unsigned short _Accum b)
{
return a + b;
}
-_Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b)
+NOMIPS16 _Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b)
{
return a + b;
}
-_Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b)
+NOMIPS16 _Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b)
{
return a + b;
}
-_Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b)
+NOMIPS16 _Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b)
{
return a + b;
}
-_Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b)
+NOMIPS16 _Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b)
{
return a + b;
}
-_Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a,
- _Sat unsigned short _Fract b)
+NOMIPS16 _Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a,
+ _Sat unsigned short _Fract b)
{
return a - b;
}
-_Sat unsigned _Fract test9 (_Sat unsigned _Fract a, _Sat unsigned _Fract b)
+NOMIPS16 _Sat unsigned _Fract test9 (_Sat unsigned _Fract a,
+ _Sat unsigned _Fract b)
{
return a - b;
}
-_Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a,
- _Sat unsigned short _Accum b)
+NOMIPS16 _Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a,
+ _Sat unsigned short _Accum b)
{
return a - b;
}
-_Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b)
+NOMIPS16 _Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b)
{
return a - b;
}
-_Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b)
+NOMIPS16 _Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b)
{
return a - b;
}
-_Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b)
+NOMIPS16 _Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b)
{
return a - b;
}
-_Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b)
+NOMIPS16 _Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b)
{
return a - b;
}
-_Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b)
+NOMIPS16 _Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b)
{
return a * b;
}
-_Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b)
+NOMIPS16 _Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b)
{
return a * b;
}
-_Fract test17 (_Fract a, _Fract b)
+NOMIPS16 _Fract test17 (_Fract a, _Fract b)
{
return a * b;
}
-long _Fract test18 (long _Fract a, long _Fract b)
+NOMIPS16 long _Fract test18 (long _Fract a, long _Fract b)
{
return a * b;
}
typedef _Fract v2hq __attribute__ ((vector_size(4)));
typedef short _Accum v2ha __attribute__ ((vector_size(4)));
-sat_v2hq test1 (sat_v2hq a, sat_v2hq b)
+NOMIPS16 sat_v2hq test1 (sat_v2hq a, sat_v2hq b)
{
return a + b;
}
-sat_v2ha test2 (sat_v2ha a, sat_v2ha b)
+NOMIPS16 sat_v2ha test2 (sat_v2ha a, sat_v2ha b)
{
return a + b;
}
-sat_v2hq test3 (sat_v2hq a, sat_v2hq b)
+NOMIPS16 sat_v2hq test3 (sat_v2hq a, sat_v2hq b)
{
return a - b;
}
-sat_v2ha test4 (sat_v2ha a, sat_v2ha b)
+NOMIPS16 sat_v2ha test4 (sat_v2ha a, sat_v2ha b)
{
return a - b;
}
-sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b)
+NOMIPS16 sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b)
{
return a + b;
}
-sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b)
+NOMIPS16 sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b)
{
return a + b;
}
-sat_v2uha test7 (sat_v2uha a, sat_v2uha b)
+NOMIPS16 sat_v2uha test7 (sat_v2uha a, sat_v2uha b)
{
return a + b;
}
-sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b)
+NOMIPS16 sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b)
{
return a - b;
}
-sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b)
+NOMIPS16 sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b)
{
return a - b;
}
-sat_v2uha test10 (sat_v2uha a, sat_v2uha b)
+NOMIPS16 sat_v2uha test10 (sat_v2uha a, sat_v2uha b)
{
return a - b;
}
-sat_v2hq test11 (sat_v2hq a, sat_v2hq b)
+NOMIPS16 sat_v2hq test11 (sat_v2hq a, sat_v2hq b)
{
return a * b;
}
-v2hq test12 (v2hq a, v2hq b)
+NOMIPS16 v2hq test12 (v2hq a, v2hq b)
{
return a + b;
}
-v2hq test13 (v2hq a, v2hq b)
+NOMIPS16 v2hq test13 (v2hq a, v2hq b)
{
return a - b;
}
-v2hq test14 (v2hq a, v2hq b)
+NOMIPS16 v2hq test14 (v2hq a, v2hq b)
{
return a * b;
}
-v2ha test15 (v2ha a, v2ha b)
+NOMIPS16 v2ha test15 (v2ha a, v2ha b)
{
return a + b;
}
-v2ha test16 (v2ha a, v2ha b)
+NOMIPS16 v2ha test16 (v2ha a, v2ha b)
{
return a - b;
}
-v4uqq test17 (v4uqq a, v4uqq b)
+NOMIPS16 v4uqq test17 (v4uqq a, v4uqq b)
{
return a + b;
}
-v4uqq test18 (v4uqq a, v4uqq b)
+NOMIPS16 v4uqq test18 (v4uqq a, v4uqq b)
{
return a - b;
}
-v2uhq test19 (v2uhq a, v2uhq b)
+NOMIPS16 v2uhq test19 (v2uhq a, v2uhq b)
{
return a + b;
}
-v2uhq test20 (v2uhq a, v2uhq b)
+NOMIPS16 v2uhq test20 (v2uhq a, v2uhq b)
{
return a - b;
}
-v2uha test21 (v2uha a, v2uha b)
+NOMIPS16 v2uha test21 (v2uha a, v2uha b)
{
return a + b;
}
-v2uha test22 (v2uha a, v2uha b)
+NOMIPS16 v2uha test22 (v2uha a, v2uha b)
{
return a - b;
}
/* { dg-mips-options "-O2 -march=vr4130 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return (long long) x * y + z;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
return z + (long long) y * x;
}
-long long
+NOMIPS16 long long
f3 (int x, int y, long long z)
{
long long t = (long long) x * y;
/* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return (long long) x * y + z;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
return z + (long long) y * x;
}
-long long
+NOMIPS16 long long
f3 (int x, int y, long long z)
{
long long t = (long long) x * y;
/* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return (long long) x * y + z;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
return z + (long long) y * x;
}
-long long
+NOMIPS16 long long
f3 (int x, int y, long long z)
{
long long t = (long long) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return (ull) x * y + z;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
return z + (ull) y * x;
}
-ull
+NOMIPS16 ull
f3 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return (ull) x * y + z;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
return z + (ull) y * x;
}
-ull
+NOMIPS16 ull
f3 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return (ull) x * y + z;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
return z + (ull) y * x;
}
-ull
+NOMIPS16 ull
f3 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
typedef float v2sf __attribute__ ((vector_size(8)));
-int main ()
+NOMIPS16 int main ()
{
int little_endian;
v2sf a, b, c, d;
typedef float v2sf __attribute__ ((vector_size(8)));
-int test0 (v2sf a, v2sf b);
-int test1 (v2sf a, v2sf b);
-int test2 (v2sf a, v2sf b);
-int test3 (v2sf a, v2sf b);
-int test4 (v2sf a, v2sf b);
-int test5 (v2sf a, v2sf b);
-int test6 (v2sf a, v2sf b);
-int test7 (v2sf a, v2sf b);
-int test8 (v2sf a, v2sf b);
-int test9 (v2sf a, v2sf b);
-int test10 (v2sf a, v2sf b);
-int test11 (v2sf a, v2sf b);
-int test12 (v2sf a, v2sf b);
-int test13 (v2sf a, v2sf b);
-int test14 (v2sf a, v2sf b);
-int test15 (v2sf a, v2sf b);
-int test16 (v2sf a, v2sf b);
-int test17 (v2sf a, v2sf b);
-int test18 (v2sf a, v2sf b);
-int test19 (v2sf a, v2sf b);
-int test20 (v2sf a, v2sf b);
-int test21 (v2sf a, v2sf b);
-int test22 (v2sf a, v2sf b);
-int test23 (v2sf a, v2sf b);
-int test24 (v2sf a, v2sf b);
-int test25 (v2sf a, v2sf b);
-int test26 (v2sf a, v2sf b);
-int test27 (v2sf a, v2sf b);
-int test28 (v2sf a, v2sf b);
-int test29 (v2sf a, v2sf b);
-int test30 (v2sf a, v2sf b);
-int test31 (v2sf a, v2sf b);
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
v2sf a, b, c, d;
int i, j;
exit (0);
}
-int test0 (v2sf a, v2sf b)
+NOMIPS16 int test0 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_f_ps (a, b);
}
-int test1 (v2sf a, v2sf b)
+NOMIPS16 int test1 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_f_ps (a, b);
}
-int test2 (v2sf a, v2sf b)
+NOMIPS16 int test2 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_un_ps (a, b);
}
-int test3 (v2sf a, v2sf b)
+NOMIPS16 int test3 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_un_ps (a, b);
}
-int test4 (v2sf a, v2sf b)
+NOMIPS16 int test4 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_eq_ps (a, b);
}
-int test5 (v2sf a, v2sf b)
+NOMIPS16 int test5 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_eq_ps (a, b);
}
-int test6 (v2sf a, v2sf b)
+NOMIPS16 int test6 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ueq_ps (a, b);
}
-int test7 (v2sf a, v2sf b)
+NOMIPS16 int test7 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ueq_ps (a, b);
}
-int test8 (v2sf a, v2sf b)
+NOMIPS16 int test8 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_olt_ps (a, b);
}
-int test9 (v2sf a, v2sf b)
+NOMIPS16 int test9 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_olt_ps (a, b);
}
-int test10 (v2sf a, v2sf b)
+NOMIPS16 int test10 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ult_ps (a, b);
}
-int test11 (v2sf a, v2sf b)
+NOMIPS16 int test11 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ult_ps (a, b);
}
-int test12 (v2sf a, v2sf b)
+NOMIPS16 int test12 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ole_ps (a, b);
}
-int test13 (v2sf a, v2sf b)
+NOMIPS16 int test13 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ole_ps (a, b);
}
-int test14 (v2sf a, v2sf b)
+NOMIPS16 int test14 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ule_ps (a, b);
}
-int test15 (v2sf a, v2sf b)
+NOMIPS16 int test15 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ule_ps (a, b);
}
-int test16 (v2sf a, v2sf b)
+NOMIPS16 int test16 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_sf_ps (a, b);
}
-int test17 (v2sf a, v2sf b)
+NOMIPS16 int test17 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_sf_ps (a, b);
}
-int test18 (v2sf a, v2sf b)
+NOMIPS16 int test18 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ngle_ps (a, b);
}
-int test19 (v2sf a, v2sf b)
+NOMIPS16 int test19 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ngle_ps (a, b);
}
-int test20 (v2sf a, v2sf b)
+NOMIPS16 int test20 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_seq_ps (a, b);
}
-int test21 (v2sf a, v2sf b)
+NOMIPS16 int test21 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_seq_ps (a, b);
}
-int test22 (v2sf a, v2sf b)
+NOMIPS16 int test22 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ngl_ps (a, b);
}
-int test23 (v2sf a, v2sf b)
+NOMIPS16 int test23 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ngl_ps (a, b);
}
-int test24 (v2sf a, v2sf b)
+NOMIPS16 int test24 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_lt_ps (a, b);
}
-int test25 (v2sf a, v2sf b)
+NOMIPS16 int test25 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_lt_ps (a, b);
}
-int test26 (v2sf a, v2sf b)
+NOMIPS16 int test26 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_nge_ps (a, b);
}
-int test27 (v2sf a, v2sf b)
+NOMIPS16 int test27 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_nge_ps (a, b);
}
-int test28 (v2sf a, v2sf b)
+NOMIPS16 int test28 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_le_ps (a, b);
}
-int test29 (v2sf a, v2sf b)
+NOMIPS16 int test29 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_le_ps (a, b);
}
-int test30 (v2sf a, v2sf b)
+NOMIPS16 int test30 (v2sf a, v2sf b)
{
return __builtin_mips_any_c_ngt_ps (a, b);
}
-int test31 (v2sf a, v2sf b)
+NOMIPS16 int test31 (v2sf a, v2sf b)
{
return __builtin_mips_all_c_ngt_ps (a, b);
}
typedef float v2sf __attribute__ ((vector_size(8)));
-int test0 (v2sf a, v2sf b);
-int test1 (v2sf a, v2sf b);
-int test2 (v2sf a, v2sf b);
-int test3 (v2sf a, v2sf b);
-int test4 (v2sf a, v2sf b);
-int test5 (v2sf a, v2sf b);
-int test6 (v2sf a, v2sf b);
-int test7 (v2sf a, v2sf b);
-int test8 (v2sf a, v2sf b);
-int test9 (v2sf a, v2sf b);
-int test10 (v2sf a, v2sf b);
-int test11 (v2sf a, v2sf b);
-int test12 (v2sf a, v2sf b);
-int test13 (v2sf a, v2sf b);
-int test14 (v2sf a, v2sf b);
-int test15 (v2sf a, v2sf b);
-int test16 (v2sf a, v2sf b);
-int test17 (v2sf a, v2sf b);
-int test18 (v2sf a, v2sf b);
-int test19 (v2sf a, v2sf b);
-int test20 (v2sf a, v2sf b);
-int test21 (v2sf a, v2sf b);
-int test22 (v2sf a, v2sf b);
-int test23 (v2sf a, v2sf b);
-int test24 (v2sf a, v2sf b);
-int test25 (v2sf a, v2sf b);
-int test26 (v2sf a, v2sf b);
-int test27 (v2sf a, v2sf b);
-int test28 (v2sf a, v2sf b);
-int test29 (v2sf a, v2sf b);
-int test30 (v2sf a, v2sf b);
-int test31 (v2sf a, v2sf b);
-int test32 (v2sf a, v2sf b);
-int test33 (v2sf a, v2sf b);
-int test34 (v2sf a, v2sf b);
-int test35 (v2sf a, v2sf b);
-int test36 (v2sf a, v2sf b);
-int test37 (v2sf a, v2sf b);
-int test38 (v2sf a, v2sf b);
-int test39 (v2sf a, v2sf b);
-int test40 (v2sf a, v2sf b);
-int test41 (v2sf a, v2sf b);
-int test42 (v2sf a, v2sf b);
-int test43 (v2sf a, v2sf b);
-int test44 (v2sf a, v2sf b);
-int test45 (v2sf a, v2sf b);
-int test46 (v2sf a, v2sf b);
-int test47 (v2sf a, v2sf b);
-int test48 (v2sf a, v2sf b);
-int test49 (v2sf a, v2sf b);
-int test50 (v2sf a, v2sf b);
-int test51 (v2sf a, v2sf b);
-int test52 (v2sf a, v2sf b);
-int test53 (v2sf a, v2sf b);
-int test54 (v2sf a, v2sf b);
-int test55 (v2sf a, v2sf b);
-int test56 (v2sf a, v2sf b);
-int test57 (v2sf a, v2sf b);
-int test58 (v2sf a, v2sf b);
-int test59 (v2sf a, v2sf b);
-int test60 (v2sf a, v2sf b);
-int test61 (v2sf a, v2sf b);
-int test62 (v2sf a, v2sf b);
-int test63 (v2sf a, v2sf b);
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+NOMIPS16 int test32 (v2sf a, v2sf b);
+NOMIPS16 int test33 (v2sf a, v2sf b);
+NOMIPS16 int test34 (v2sf a, v2sf b);
+NOMIPS16 int test35 (v2sf a, v2sf b);
+NOMIPS16 int test36 (v2sf a, v2sf b);
+NOMIPS16 int test37 (v2sf a, v2sf b);
+NOMIPS16 int test38 (v2sf a, v2sf b);
+NOMIPS16 int test39 (v2sf a, v2sf b);
+NOMIPS16 int test40 (v2sf a, v2sf b);
+NOMIPS16 int test41 (v2sf a, v2sf b);
+NOMIPS16 int test42 (v2sf a, v2sf b);
+NOMIPS16 int test43 (v2sf a, v2sf b);
+NOMIPS16 int test44 (v2sf a, v2sf b);
+NOMIPS16 int test45 (v2sf a, v2sf b);
+NOMIPS16 int test46 (v2sf a, v2sf b);
+NOMIPS16 int test47 (v2sf a, v2sf b);
+NOMIPS16 int test48 (v2sf a, v2sf b);
+NOMIPS16 int test49 (v2sf a, v2sf b);
+NOMIPS16 int test50 (v2sf a, v2sf b);
+NOMIPS16 int test51 (v2sf a, v2sf b);
+NOMIPS16 int test52 (v2sf a, v2sf b);
+NOMIPS16 int test53 (v2sf a, v2sf b);
+NOMIPS16 int test54 (v2sf a, v2sf b);
+NOMIPS16 int test55 (v2sf a, v2sf b);
+NOMIPS16 int test56 (v2sf a, v2sf b);
+NOMIPS16 int test57 (v2sf a, v2sf b);
+NOMIPS16 int test58 (v2sf a, v2sf b);
+NOMIPS16 int test59 (v2sf a, v2sf b);
+NOMIPS16 int test60 (v2sf a, v2sf b);
+NOMIPS16 int test61 (v2sf a, v2sf b);
+NOMIPS16 int test62 (v2sf a, v2sf b);
+NOMIPS16 int test63 (v2sf a, v2sf b);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
int little_endian;
v2sf a, b, c, d;
exit (0);
}
-int test0 (v2sf a, v2sf b)
+NOMIPS16 int test0 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_f_ps (a, b);
}
-int test1 (v2sf a, v2sf b)
+NOMIPS16 int test1 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_f_ps (a, b);
}
-int test2 (v2sf a, v2sf b)
+NOMIPS16 int test2 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_f_ps (a, b);
}
-int test3 (v2sf a, v2sf b)
+NOMIPS16 int test3 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_f_ps (a, b);
}
-int test4 (v2sf a, v2sf b)
+NOMIPS16 int test4 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_un_ps (a, b);
}
-int test5 (v2sf a, v2sf b)
+NOMIPS16 int test5 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_un_ps (a, b);
}
-int test6 (v2sf a, v2sf b)
+NOMIPS16 int test6 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_un_ps (a, b);
}
-int test7 (v2sf a, v2sf b)
+NOMIPS16 int test7 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_un_ps (a, b);
}
-int test8 (v2sf a, v2sf b)
+NOMIPS16 int test8 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_eq_ps (a, b);
}
-int test9 (v2sf a, v2sf b)
+NOMIPS16 int test9 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_eq_ps (a, b);
}
-int test10 (v2sf a, v2sf b)
+NOMIPS16 int test10 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_eq_ps (a, b);
}
-int test11 (v2sf a, v2sf b)
+NOMIPS16 int test11 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_eq_ps (a, b);
}
-int test12 (v2sf a, v2sf b)
+NOMIPS16 int test12 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ueq_ps (a, b);
}
-int test13 (v2sf a, v2sf b)
+NOMIPS16 int test13 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ueq_ps (a, b);
}
-int test14 (v2sf a, v2sf b)
+NOMIPS16 int test14 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ueq_ps (a, b);
}
-int test15 (v2sf a, v2sf b)
+NOMIPS16 int test15 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ueq_ps (a, b);
}
-int test16 (v2sf a, v2sf b)
+NOMIPS16 int test16 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_olt_ps (a, b);
}
-int test17 (v2sf a, v2sf b)
+NOMIPS16 int test17 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_olt_ps (a, b);
}
-int test18 (v2sf a, v2sf b)
+NOMIPS16 int test18 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_olt_ps (a, b);
}
-int test19 (v2sf a, v2sf b)
+NOMIPS16 int test19 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_olt_ps (a, b);
}
-int test20 (v2sf a, v2sf b)
+NOMIPS16 int test20 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ult_ps (a, b);
}
-int test21 (v2sf a, v2sf b)
+NOMIPS16 int test21 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ult_ps (a, b);
}
-int test22 (v2sf a, v2sf b)
+NOMIPS16 int test22 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ult_ps (a, b);
}
-int test23 (v2sf a, v2sf b)
+NOMIPS16 int test23 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ult_ps (a, b);
}
-int test24 (v2sf a, v2sf b)
+NOMIPS16 int test24 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ole_ps (a, b);
}
-int test25 (v2sf a, v2sf b)
+NOMIPS16 int test25 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ole_ps (a, b);
}
-int test26 (v2sf a, v2sf b)
+NOMIPS16 int test26 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ole_ps (a, b);
}
-int test27 (v2sf a, v2sf b)
+NOMIPS16 int test27 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ole_ps (a, b);
}
-int test28 (v2sf a, v2sf b)
+NOMIPS16 int test28 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ule_ps (a, b);
}
-int test29 (v2sf a, v2sf b)
+NOMIPS16 int test29 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ule_ps (a, b);
}
-int test30 (v2sf a, v2sf b)
+NOMIPS16 int test30 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ule_ps (a, b);
}
-int test31 (v2sf a, v2sf b)
+NOMIPS16 int test31 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ule_ps (a, b);
}
-int test32 (v2sf a, v2sf b)
+NOMIPS16 int test32 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_sf_ps (a, b);
}
-int test33 (v2sf a, v2sf b)
+NOMIPS16 int test33 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_sf_ps (a, b);
}
-int test34 (v2sf a, v2sf b)
+NOMIPS16 int test34 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_sf_ps (a, b);
}
-int test35 (v2sf a, v2sf b)
+NOMIPS16 int test35 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_sf_ps (a, b);
}
-int test36 (v2sf a, v2sf b)
+NOMIPS16 int test36 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ngle_ps (a, b);
}
-int test37 (v2sf a, v2sf b)
+NOMIPS16 int test37 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ngle_ps (a, b);
}
-int test38 (v2sf a, v2sf b)
+NOMIPS16 int test38 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ngle_ps (a, b);
}
-int test39 (v2sf a, v2sf b)
+NOMIPS16 int test39 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ngle_ps (a, b);
}
-int test40 (v2sf a, v2sf b)
+NOMIPS16 int test40 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_seq_ps (a, b);
}
-int test41 (v2sf a, v2sf b)
+NOMIPS16 int test41 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_seq_ps (a, b);
}
-int test42 (v2sf a, v2sf b)
+NOMIPS16 int test42 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_seq_ps (a, b);
}
-int test43 (v2sf a, v2sf b)
+NOMIPS16 int test43 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_seq_ps (a, b);
}
-int test44 (v2sf a, v2sf b)
+NOMIPS16 int test44 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ngl_ps (a, b);
}
-int test45 (v2sf a, v2sf b)
+NOMIPS16 int test45 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ngl_ps (a, b);
}
-int test46 (v2sf a, v2sf b)
+NOMIPS16 int test46 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ngl_ps (a, b);
}
-int test47 (v2sf a, v2sf b)
+NOMIPS16 int test47 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ngl_ps (a, b);
}
-int test48 (v2sf a, v2sf b)
+NOMIPS16 int test48 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_lt_ps (a, b);
}
-int test49 (v2sf a, v2sf b)
+NOMIPS16 int test49 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_lt_ps (a, b);
}
-int test50 (v2sf a, v2sf b)
+NOMIPS16 int test50 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_lt_ps (a, b);
}
-int test51 (v2sf a, v2sf b)
+NOMIPS16 int test51 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_lt_ps (a, b);
}
-int test52 (v2sf a, v2sf b)
+NOMIPS16 int test52 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_nge_ps (a, b);
}
-int test53 (v2sf a, v2sf b)
+NOMIPS16 int test53 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_nge_ps (a, b);
}
-int test54 (v2sf a, v2sf b)
+NOMIPS16 int test54 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_nge_ps (a, b);
}
-int test55 (v2sf a, v2sf b)
+NOMIPS16 int test55 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_nge_ps (a, b);
}
-int test56 (v2sf a, v2sf b)
+NOMIPS16 int test56 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_le_ps (a, b);
}
-int test57 (v2sf a, v2sf b)
+NOMIPS16 int test57 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_le_ps (a, b);
}
-int test58 (v2sf a, v2sf b)
+NOMIPS16 int test58 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_le_ps (a, b);
}
-int test59 (v2sf a, v2sf b)
+NOMIPS16 int test59 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_le_ps (a, b);
}
-int test60 (v2sf a, v2sf b)
+NOMIPS16 int test60 (v2sf a, v2sf b)
{
return __builtin_mips_any_cabs_ngt_ps (a, b);
}
-int test61 (v2sf a, v2sf b)
+NOMIPS16 int test61 (v2sf a, v2sf b)
{
return __builtin_mips_upper_cabs_ngt_ps (a, b);
}
-int test62 (v2sf a, v2sf b)
+NOMIPS16 int test62 (v2sf a, v2sf b)
{
return __builtin_mips_lower_cabs_ngt_ps (a, b);
}
-int test63 (v2sf a, v2sf b)
+NOMIPS16 int test63 (v2sf a, v2sf b)
{
return __builtin_mips_all_cabs_ngt_ps (a, b);
}
typedef float v2sf __attribute__ ((vector_size(8)));
-int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
v2sf a, b, c, d;
int i, j;
exit (0);
}
-int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_f_4s (a, b, c, d);
}
-int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_f_4s (a, b, c, d);
}
-int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_un_4s (a, b, c, d);
}
-int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_un_4s (a, b, c, d);
}
-int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_eq_4s (a, b, c, d);
}
-int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_eq_4s (a, b, c, d);
}
-int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ueq_4s (a, b, c, d);
}
-int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ueq_4s (a, b, c, d);
}
-int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_olt_4s (a, b, c, d);
}
-int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_olt_4s (a, b, c, d);
}
-int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ult_4s (a, b, c, d);
}
-int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ult_4s (a, b, c, d);
}
-int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ole_4s (a, b, c, d);
}
-int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ole_4s (a, b, c, d);
}
-int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ule_4s (a, b, c, d);
}
-int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ule_4s (a, b, c, d);
}
-int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_sf_4s (a, b, c, d);
}
-int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_sf_4s (a, b, c, d);
}
-int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ngle_4s (a, b, c, d);
}
-int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ngle_4s (a, b, c, d);
}
-int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_seq_4s (a, b, c, d);
}
-int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_seq_4s (a, b, c, d);
}
-int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ngl_4s (a, b, c, d);
}
-int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ngl_4s (a, b, c, d);
}
-int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_lt_4s (a, b, c, d);
}
-int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_lt_4s (a, b, c, d);
}
-int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_nge_4s (a, b, c, d);
}
-int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_nge_4s (a, b, c, d);
}
-int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_le_4s (a, b, c, d);
}
-int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_le_4s (a, b, c, d);
}
-int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_c_ngt_4s (a, b, c, d);
}
-int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_c_ngt_4s (a, b, c, d);
}
typedef float v2sf __attribute__ ((vector_size(8)));
-int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
-int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
v2sf a, b, c, d;
int i, j;
exit (0);
}
-int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_f_4s (a, b, c, d);
}
-int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_f_4s (a, b, c, d);
}
-int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_un_4s (a, b, c, d);
}
-int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_un_4s (a, b, c, d);
}
-int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_eq_4s (a, b, c, d);
}
-int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_eq_4s (a, b, c, d);
}
-int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ueq_4s (a, b, c, d);
}
-int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ueq_4s (a, b, c, d);
}
-int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_olt_4s (a, b, c, d);
}
-int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_olt_4s (a, b, c, d);
}
-int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ult_4s (a, b, c, d);
}
-int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ult_4s (a, b, c, d);
}
-int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ole_4s (a, b, c, d);
}
-int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ole_4s (a, b, c, d);
}
-int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ule_4s (a, b, c, d);
}
-int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ule_4s (a, b, c, d);
}
-int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_sf_4s (a, b, c, d);
}
-int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_sf_4s (a, b, c, d);
}
-int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ngle_4s (a, b, c, d);
}
-int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ngle_4s (a, b, c, d);
}
-int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_seq_4s (a, b, c, d);
}
-int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_seq_4s (a, b, c, d);
}
-int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ngl_4s (a, b, c, d);
}
-int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ngl_4s (a, b, c, d);
}
-int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_lt_4s (a, b, c, d);
}
-int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_lt_4s (a, b, c, d);
}
-int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_nge_4s (a, b, c, d);
}
-int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_nge_4s (a, b, c, d);
}
-int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_le_4s (a, b, c, d);
}
-int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_le_4s (a, b, c, d);
}
-int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_any_cabs_ngt_4s (a, b, c, d);
}
-int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_all_cabs_ngt_4s (a, b, c, d);
}
#include <stdlib.h>
#include <stdio.h>
-int test0 (float a, float b);
-int test1 (float a, float b);
-int test2 (float a, float b);
-int test3 (float a, float b);
-int test4 (float a, float b);
-int test5 (float a, float b);
-int test6 (float a, float b);
-int test7 (float a, float b);
-int test8 (float a, float b);
-int test9 (float a, float b);
-int test10 (float a, float b);
-int test11 (float a, float b);
-int test12 (float a, float b);
-int test13 (float a, float b);
-int test14 (float a, float b);
-int test15 (float a, float b);
+NOMIPS16 int test0 (float a, float b);
+NOMIPS16 int test1 (float a, float b);
+NOMIPS16 int test2 (float a, float b);
+NOMIPS16 int test3 (float a, float b);
+NOMIPS16 int test4 (float a, float b);
+NOMIPS16 int test5 (float a, float b);
+NOMIPS16 int test6 (float a, float b);
+NOMIPS16 int test7 (float a, float b);
+NOMIPS16 int test8 (float a, float b);
+NOMIPS16 int test9 (float a, float b);
+NOMIPS16 int test10 (float a, float b);
+NOMIPS16 int test11 (float a, float b);
+NOMIPS16 int test12 (float a, float b);
+NOMIPS16 int test13 (float a, float b);
+NOMIPS16 int test14 (float a, float b);
+NOMIPS16 int test15 (float a, float b);
-int main ()
+NOMIPS16 int main ()
{
float a, b;
int i;
exit (0);
}
-int test0 (float a, float b)
+NOMIPS16 int test0 (float a, float b)
{
return __builtin_mips_cabs_f_s (a, b);
}
-int test1 (float a, float b)
+NOMIPS16 int test1 (float a, float b)
{
return __builtin_mips_cabs_un_s (a, b);
}
-int test2 (float a, float b)
+NOMIPS16 int test2 (float a, float b)
{
return __builtin_mips_cabs_eq_s (a, b);
}
-int test3 (float a, float b)
+NOMIPS16 int test3 (float a, float b)
{
return __builtin_mips_cabs_ueq_s (a, b);
}
-int test4 (float a, float b)
+NOMIPS16 int test4 (float a, float b)
{
return __builtin_mips_cabs_olt_s (a, b);
}
-int test5 (float a, float b)
+NOMIPS16 int test5 (float a, float b)
{
return __builtin_mips_cabs_ult_s (a, b);
}
-int test6 (float a, float b)
+NOMIPS16 int test6 (float a, float b)
{
return __builtin_mips_cabs_ole_s (a, b);
}
-int test7 (float a, float b)
+NOMIPS16 int test7 (float a, float b)
{
return __builtin_mips_cabs_ule_s (a, b);
}
-int test8 (float a, float b)
+NOMIPS16 int test8 (float a, float b)
{
return __builtin_mips_cabs_sf_s (a, b);
}
-int test9 (float a, float b)
+NOMIPS16 int test9 (float a, float b)
{
return __builtin_mips_cabs_ngle_s (a, b);
}
-int test10 (float a, float b)
+NOMIPS16 int test10 (float a, float b)
{
return __builtin_mips_cabs_seq_s (a, b);
}
-int test11 (float a, float b)
+NOMIPS16 int test11 (float a, float b)
{
return __builtin_mips_cabs_ngl_s (a, b);
}
-int test12 (float a, float b)
+NOMIPS16 int test12 (float a, float b)
{
return __builtin_mips_cabs_lt_s (a, b);
}
-int test13 (float a, float b)
+NOMIPS16 int test13 (float a, float b)
{
return __builtin_mips_cabs_nge_s (a, b);
}
-int test14 (float a, float b)
+NOMIPS16 int test14 (float a, float b)
{
return __builtin_mips_cabs_le_s (a, b);
}
-int test15 (float a, float b)
+NOMIPS16 int test15 (float a, float b)
{
return __builtin_mips_cabs_ngt_s (a, b);
}
#include <stdlib.h>
#include <stdio.h>
-int test0 (double a, double b);
-int test1 (double a, double b);
-int test2 (double a, double b);
-int test3 (double a, double b);
-int test4 (double a, double b);
-int test5 (double a, double b);
-int test6 (double a, double b);
-int test7 (double a, double b);
-int test8 (double a, double b);
-int test9 (double a, double b);
-int test10 (double a, double b);
-int test11 (double a, double b);
-int test12 (double a, double b);
-int test13 (double a, double b);
-int test14 (double a, double b);
-int test15 (double a, double b);
+NOMIPS16 int test0 (double a, double b);
+NOMIPS16 int test1 (double a, double b);
+NOMIPS16 int test2 (double a, double b);
+NOMIPS16 int test3 (double a, double b);
+NOMIPS16 int test4 (double a, double b);
+NOMIPS16 int test5 (double a, double b);
+NOMIPS16 int test6 (double a, double b);
+NOMIPS16 int test7 (double a, double b);
+NOMIPS16 int test8 (double a, double b);
+NOMIPS16 int test9 (double a, double b);
+NOMIPS16 int test10 (double a, double b);
+NOMIPS16 int test11 (double a, double b);
+NOMIPS16 int test12 (double a, double b);
+NOMIPS16 int test13 (double a, double b);
+NOMIPS16 int test14 (double a, double b);
+NOMIPS16 int test15 (double a, double b);
-int main ()
+NOMIPS16 int main ()
{
double a, b;
int i;
exit (0);
}
-int test0 (double a, double b)
+NOMIPS16 int test0 (double a, double b)
{
return __builtin_mips_cabs_f_d (a, b);
}
-int test1 (double a, double b)
+NOMIPS16 int test1 (double a, double b)
{
return __builtin_mips_cabs_un_d (a, b);
}
-int test2 (double a, double b)
+NOMIPS16 int test2 (double a, double b)
{
return __builtin_mips_cabs_eq_d (a, b);
}
-int test3 (double a, double b)
+NOMIPS16 int test3 (double a, double b)
{
return __builtin_mips_cabs_ueq_d (a, b);
}
-int test4 (double a, double b)
+NOMIPS16 int test4 (double a, double b)
{
return __builtin_mips_cabs_olt_d (a, b);
}
-int test5 (double a, double b)
+NOMIPS16 int test5 (double a, double b)
{
return __builtin_mips_cabs_ult_d (a, b);
}
-int test6 (double a, double b)
+NOMIPS16 int test6 (double a, double b)
{
return __builtin_mips_cabs_ole_d (a, b);
}
-int test7 (double a, double b)
+NOMIPS16 int test7 (double a, double b)
{
return __builtin_mips_cabs_ule_d (a, b);
}
-int test8 (double a, double b)
+NOMIPS16 int test8 (double a, double b)
{
return __builtin_mips_cabs_sf_d (a, b);
}
-int test9 (double a, double b)
+NOMIPS16 int test9 (double a, double b)
{
return __builtin_mips_cabs_ngle_d (a, b);
}
-int test10 (double a, double b)
+NOMIPS16 int test10 (double a, double b)
{
return __builtin_mips_cabs_seq_d (a, b);
}
-int test11 (double a, double b)
+NOMIPS16 int test11 (double a, double b)
{
return __builtin_mips_cabs_ngl_d (a, b);
}
-int test12 (double a, double b)
+NOMIPS16 int test12 (double a, double b)
{
return __builtin_mips_cabs_lt_d (a, b);
}
-int test13 (double a, double b)
+NOMIPS16 int test13 (double a, double b)
{
return __builtin_mips_cabs_nge_d (a, b);
}
-int test14 (double a, double b)
+NOMIPS16 int test14 (double a, double b)
{
return __builtin_mips_cabs_le_d (a, b);
}
-int test15 (double a, double b)
+NOMIPS16 int test15 (double a, double b)
{
return __builtin_mips_cabs_ngt_d (a, b);
}
typedef float v2sf __attribute__((vector_size(8)));
-v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
v2sf a, b, c, d, e, f;
exit (0);
}
-v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_f_ps (a, b, c, d);
}
-v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_f_ps (a, b, c, d);
}
-v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_un_ps (a, b, c, d);
}
-v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_un_ps (a, b, c, d);
}
-v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
}
-v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
}
-v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ueq_ps (a, b, c, d);
}
-v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ueq_ps (a, b, c, d);
}
-v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_olt_ps (a, b, c, d);
}
-v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_olt_ps (a, b, c, d);
}
-v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ult_ps (a, b, c, d);
}
-v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ult_ps (a, b, c, d);
}
-v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ole_ps (a, b, c, d);
}
-v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ole_ps (a, b, c, d);
}
-v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ule_ps (a, b, c, d);
}
-v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ule_ps (a, b, c, d);
}
-v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_sf_ps (a, b, c, d);
}
-v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_sf_ps (a, b, c, d);
}
-v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ngle_ps (a, b, c, d);
}
-v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ngle_ps (a, b, c, d);
}
-v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_seq_ps (a, b, c, d);
}
-v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_seq_ps (a, b, c, d);
}
-v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ngl_ps (a, b, c, d);
}
-v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ngl_ps (a, b, c, d);
}
-v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_lt_ps (a, b, c, d);
}
-v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_lt_ps (a, b, c, d);
}
-v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_nge_ps (a, b, c, d);
}
-v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_nge_ps (a, b, c, d);
}
-v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_le_ps (a, b, c, d);
}
-v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_le_ps (a, b, c, d);
}
-v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_cabs_ngt_ps (a, b, c, d);
}
-v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_cabs_ngt_ps (a, b, c, d);
}
float f[4]; /* Result for matrix_multiply4() */
void matrix_multiply1();
-void matrix_multiply2();
-void matrix_multiply3();
-void matrix_multiply4();
+NOMIPS16 void matrix_multiply2();
+NOMIPS16 void matrix_multiply3();
+NOMIPS16 void matrix_multiply4();
int main ()
{
}
}
-void matrix_multiply2()
+NOMIPS16 void matrix_multiply2()
{
int i, j;
v2sf m1, m2;
}
}
-void matrix_multiply3()
+NOMIPS16 void matrix_multiply3()
{
int i;
v2sf m1, m2, n1, n2;
}
}
-void matrix_multiply4()
+NOMIPS16 void matrix_multiply4()
{
v2sf m1, m2;
v2sf n1, n2, n3, n4, n5, n6, n7, n8;
return b;
}
-int main()
+NOMIPS16 int main()
{
v2sf a, b, c, d, e, f;
float f1, f2;
typedef float v2sf __attribute__ ((vector_size(8)));
-int main ()
+NOMIPS16 int main ()
{
int little_endian;
v2sf a, b, c, d;
typedef float v2sf __attribute__((vector_size(8)));
-v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
-v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main ()
+NOMIPS16 int main ()
{
float f1;
v2sf a, b, c, d, e, f;
exit (0);
}
-v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_f_ps (a, b, c, d);
}
-v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_f_ps (a, b, c, d);
}
-v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_un_ps (a, b, c, d);
}
-v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_un_ps (a, b, c, d);
}
-v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_eq_ps (a, b, c, d);
}
-v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_eq_ps (a, b, c, d);
}
-v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ueq_ps (a, b, c, d);
}
-v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ueq_ps (a, b, c, d);
}
-v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_olt_ps (a, b, c, d);
}
-v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_olt_ps (a, b, c, d);
}
-v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ult_ps (a, b, c, d);
}
-v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ult_ps (a, b, c, d);
}
-v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ole_ps (a, b, c, d);
}
-v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ole_ps (a, b, c, d);
}
-v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ule_ps (a, b, c, d);
}
-v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ule_ps (a, b, c, d);
}
-v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_sf_ps (a, b, c, d);
}
-v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_sf_ps (a, b, c, d);
}
-v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ngle_ps (a, b, c, d);
}
-v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ngle_ps (a, b, c, d);
}
-v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_seq_ps (a, b, c, d);
}
-v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_seq_ps (a, b, c, d);
}
-v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ngl_ps (a, b, c, d);
}
-v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ngl_ps (a, b, c, d);
}
-v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_lt_ps (a, b, c, d);
}
-v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_lt_ps (a, b, c, d);
}
-v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_nge_ps (a, b, c, d);
}
-v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_nge_ps (a, b, c, d);
}
-v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_le_ps (a, b, c, d);
}
-v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_le_ps (a, b, c, d);
}
-v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movt_c_ngt_ps (a, b, c, d);
}
-v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
{
return __builtin_mips_movf_c_ngt_ps (a, b, c, d);
}
typedef float v2sf __attribute__((vector_size(8)));
-int test0 (v2sf a, v2sf b);
-int test1 (v2sf a, v2sf b);
-int test2 (v2sf a, v2sf b);
-int test3 (v2sf a, v2sf b);
-int test4 (v2sf a, v2sf b);
-int test5 (v2sf a, v2sf b);
-int test6 (v2sf a, v2sf b);
-int test7 (v2sf a, v2sf b);
-int test8 (v2sf a, v2sf b);
-int test9 (v2sf a, v2sf b);
-int test10 (v2sf a, v2sf b);
-int test11 (v2sf a, v2sf b);
-int test12 (v2sf a, v2sf b);
-int test13 (v2sf a, v2sf b);
-int test14 (v2sf a, v2sf b);
-int test15 (v2sf a, v2sf b);
-int test16 (v2sf a, v2sf b);
-int test17 (v2sf a, v2sf b);
-int test18 (v2sf a, v2sf b);
-int test19 (v2sf a, v2sf b);
-int test20 (v2sf a, v2sf b);
-int test21 (v2sf a, v2sf b);
-int test22 (v2sf a, v2sf b);
-int test23 (v2sf a, v2sf b);
-int test24 (v2sf a, v2sf b);
-int test25 (v2sf a, v2sf b);
-int test26 (v2sf a, v2sf b);
-int test27 (v2sf a, v2sf b);
-int test28 (v2sf a, v2sf b);
-int test29 (v2sf a, v2sf b);
-int test30 (v2sf a, v2sf b);
-int test31 (v2sf a, v2sf b);
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
float qnan = 1.0f/0.0f - 1.0f/0.0f;
-int main()
+NOMIPS16 int main()
{
union { long long ll; int i[2]; } endianness_test;
int little_endian;
exit (0);
}
-int test0 (v2sf a, v2sf b)
+NOMIPS16 int test0 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_f_ps (a, b);
}
-int test1 (v2sf a, v2sf b)
+NOMIPS16 int test1 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_f_ps (a, b);
}
-int test2 (v2sf a, v2sf b)
+NOMIPS16 int test2 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_un_ps (a, b);
}
-int test3 (v2sf a, v2sf b)
+NOMIPS16 int test3 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_un_ps (a, b);
}
-int test4 (v2sf a, v2sf b)
+NOMIPS16 int test4 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_eq_ps (a, b);
}
-int test5 (v2sf a, v2sf b)
+NOMIPS16 int test5 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_eq_ps (a, b);
}
-int test6 (v2sf a, v2sf b)
+NOMIPS16 int test6 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ueq_ps (a, b);
}
-int test7 (v2sf a, v2sf b)
+NOMIPS16 int test7 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ueq_ps (a, b);
}
-int test8 (v2sf a, v2sf b)
+NOMIPS16 int test8 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_olt_ps (a, b);
}
-int test9 (v2sf a, v2sf b)
+NOMIPS16 int test9 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_olt_ps (a, b);
}
-int test10 (v2sf a, v2sf b)
+NOMIPS16 int test10 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ult_ps (a, b);
}
-int test11 (v2sf a, v2sf b)
+NOMIPS16 int test11 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ult_ps (a, b);
}
-int test12 (v2sf a, v2sf b)
+NOMIPS16 int test12 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ole_ps (a, b);
}
-int test13 (v2sf a, v2sf b)
+NOMIPS16 int test13 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ole_ps (a, b);
}
-int test14 (v2sf a, v2sf b)
+NOMIPS16 int test14 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ule_ps (a, b);
}
-int test15 (v2sf a, v2sf b)
+NOMIPS16 int test15 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ule_ps (a, b);
}
-int test16 (v2sf a, v2sf b)
+NOMIPS16 int test16 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_sf_ps (a, b);
}
-int test17 (v2sf a, v2sf b)
+NOMIPS16 int test17 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_sf_ps (a, b);
}
-int test18 (v2sf a, v2sf b)
+NOMIPS16 int test18 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ngle_ps (a, b);
}
-int test19 (v2sf a, v2sf b)
+NOMIPS16 int test19 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ngle_ps (a, b);
}
-int test20 (v2sf a, v2sf b)
+NOMIPS16 int test20 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_seq_ps (a, b);
}
-int test21 (v2sf a, v2sf b)
+NOMIPS16 int test21 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_seq_ps (a, b);
}
-int test22 (v2sf a, v2sf b)
+NOMIPS16 int test22 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ngl_ps (a, b);
}
-int test23 (v2sf a, v2sf b)
+NOMIPS16 int test23 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ngl_ps (a, b);
}
-int test24 (v2sf a, v2sf b)
+NOMIPS16 int test24 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_lt_ps (a, b);
}
-int test25 (v2sf a, v2sf b)
+NOMIPS16 int test25 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_lt_ps (a, b);
}
-int test26 (v2sf a, v2sf b)
+NOMIPS16 int test26 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_nge_ps (a, b);
}
-int test27 (v2sf a, v2sf b)
+NOMIPS16 int test27 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_nge_ps (a, b);
}
-int test28 (v2sf a, v2sf b)
+NOMIPS16 int test28 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_le_ps (a, b);
}
-int test29 (v2sf a, v2sf b)
+NOMIPS16 int test29 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_le_ps (a, b);
}
-int test30 (v2sf a, v2sf b)
+NOMIPS16 int test30 (v2sf a, v2sf b)
{
return __builtin_mips_upper_c_ngt_ps (a, b);
}
-int test31 (v2sf a, v2sf b)
+NOMIPS16 int test31 (v2sf a, v2sf b)
{
return __builtin_mips_lower_c_ngt_ps (a, b);
}
extern float a[], b[], c[];
-void
+NOMIPS16 void
foo (void)
{
int i;
typedef float v2sf __attribute__ ((vector_size(8)));
-int main ()
+NOMIPS16 int main ()
{
int little_endian;
v2sf a, b, c, d;
v2sf A = {100, 200};
/* Init from floats */
-v2sf init (float a, float b)
+NOMIPS16 v2sf init (float a, float b)
{
return (v2sf) {a, b};
}
/* Move between registers */
-v2sf move (v2sf a)
+NOMIPS16 v2sf move (v2sf a)
{
return a;
}
/* Load from memory */
-v2sf load ()
+NOMIPS16 v2sf load ()
{
return A;
}
/* Store to memory */
-void store (v2sf a)
+NOMIPS16 void store (v2sf a)
{
A = a;
}
/* Add */
-v2sf add (v2sf a, v2sf b)
+NOMIPS16 v2sf add (v2sf a, v2sf b)
{
return a + b;
}
/* Subtract */
-v2sf sub (v2sf a, v2sf b)
+NOMIPS16 v2sf sub (v2sf a, v2sf b)
{
return a - b;
}
/* Negate */
-v2sf neg (v2sf a)
+NOMIPS16 v2sf neg (v2sf a)
{
return - a;
}
/* Multiply */
-v2sf mul (v2sf a, v2sf b)
+NOMIPS16 v2sf mul (v2sf a, v2sf b)
{
return a * b;
}
/* Multiply and add */
-v2sf madd (v2sf a, v2sf b, v2sf c)
+NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c)
{
return a * b + c;
}
/* Multiply and subtract */
-v2sf msub (v2sf a, v2sf b, v2sf c)
+NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c)
{
return a * b - c;
}
/* Negate Multiply and add */
-v2sf nmadd (v2sf a, v2sf b, v2sf c)
+NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c)
{
return - (a * b + c);
}
/* Negate Multiply and subtract */
-v2sf nmsub (v2sf a, v2sf b, v2sf c)
+NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c)
{
return - (a * b - c);
}
/* Conditional Move */
-v2sf cond_move1 (v2sf a, v2sf b, long i)
+NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, long i)
{
if (i > 0)
return a;
}
/* Conditional Move */
-v2sf cond_move2 (v2sf a, v2sf b, int i)
+NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i)
{
if (i > 0)
return a;
#
# $mips_isa: the ISA level specified by __mips
# $mips_arch: the architecture specified by _MIPS_ARCH
-# $mips_mips16: true if MIPS16 mode is selected
# $mips_gp64: true if 64-bit output is selected
# $mips_fp64: true if 64-bit FPRs are selected
# $mips_float: "hard" or "soft"
proc setup_mips_tests {} {
global mips_isa
global mips_arch
- global mips_mips16
global mips_gp64
global mips_fp64
global mips_float
puts $f {
int isa = __mips;
const char *arch = _MIPS_ARCH;
- #ifdef __mips16
- int mips16 = 1;
- #endif
#ifdef __mips64
int gp64 = 1;
#endif
regexp {isa = ([^;]*)} $output dummy mips_isa
regexp {arch = "([^"]*)} $output dummy mips_arch
- set mips_mips16 [regexp {mips16 = 1} $output]
set mips_gp64 [regexp {gp64 = 1} $output]
set mips_fp64 [regexp {fp64 = 1} $output]
regexp {float = "([^"]*)} $output dummy mips_float
- set mips_forced_isa [regexp -- {(-mips|-march)} $compiler_flags]
+ set mips_forced_isa [regexp -- {(-mips[1-5][[:>:]]|-mips32*|-mips64*|-march)} $compiler_flags]
set mips_forced_abi [regexp -- {(-mgp|-mfp|-mabi)} $compiler_flags]
set mips_forced_float [regexp -- {-m(hard|soft)-float} $compiler_flags]
set mips_forced_le [regexp -- {-(EL|mel)[[:>:]]} $compiler_flags]
#
# -march=*
# -mips*
-# Select the target architecture. Skip the test for MIPS16 targets
-# or if the multilib flags force a different architecture.
+# Select the target architecture. Skip the test if the multilib
+# flags force a different architecture.
#
# -msoft-float
# -mhard-float
global mips_isa
global mips_arch
- global mips_mips16
global mips_gp64
global mips_fp64
global mips_float
set matches 0
}
} elseif {[regexp -- {^-march=(.*)} $flag dummy arch]} {
- if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} {
+ if {$arch != $mips_arch && $mips_forced_isa} {
set matches 0
}
} elseif {[regexp -- {^-mips(.*)} $flag dummy isa] && $isa != 16} {
- if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} {
+ if {$isa != $mips_isa && $mips_forced_isa} {
set matches 0
}
} elseif {[regexp -- {^-m(hard|soft)-float} $flag dummy float]} {
typedef char v4qi __attribute__ ((vector_size(4)));
typedef short v2hi __attribute__ ((vector_size(4)));
-v2hi add_v2hi (v2hi a, v2hi b)
+NOMIPS16 v2hi add_v2hi (v2hi a, v2hi b)
{
return a + b;
}
-v4qi add_v4qi (v4qi a, v4qi b)
+NOMIPS16 v4qi add_v4qi (v4qi a, v4qi b)
{
return a + b;
}
-v2hi sub_v2hi (v2hi a, v2hi b)
+NOMIPS16 v2hi sub_v2hi (v2hi a, v2hi b)
{
return a - b;
}
-v4qi sub_v4qi (v4qi a, v4qi b)
+NOMIPS16 v4qi sub_v4qi (v4qi a, v4qi b)
{
return a - b;
}
typedef int i32;
typedef long long a64;
-void test_MIPS_DSP (void);
+NOMIPS16 void test_MIPS_DSP (void);
char array[100];
int little_endian;
exit (0);
}
-v2q15 add_v2q15 (v2q15 a, v2q15 b)
+NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
{
return __builtin_mips_addq_ph (a, b);
}
-v4i8 add_v4i8 (v4i8 a, v4i8 b)
+NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
{
return __builtin_mips_addu_qb (a, b);
}
-v2q15 sub_v2q15 (v2q15 a, v2q15 b)
+NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
{
return __builtin_mips_subq_ph (a, b);
}
-v4i8 sub_v4i8 (v4i8 a, v4i8 b)
+NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
{
return __builtin_mips_subu_qb (a, b);
}
-void test_MIPS_DSP ()
+NOMIPS16 void test_MIPS_DSP ()
{
v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
void ext_int (int);
-int
+NOMIPS16 int
sub1 (int i, int j, int k)
{
ext_int (k ? i : j);
}
-int
+NOMIPS16 int
sub2 (int i, int j, long l)
{
ext_int (!l ? i : j);
void ext_long (long);
-long
+NOMIPS16 long
sub4 (long i, long j, long k)
{
ext_long (k ? i : j);
}
-long
+NOMIPS16 long
sub5 (long i, long j, int k)
{
ext_long (!k ? i : j);
void ext_float (float);
void ext_double (double);
-int
+NOMIPS16 int
sub3 (int i, int j, float f)
{
ext_int (f ? i : j);
}
-long
+NOMIPS16 long
sub6 (long i, long j, float f)
{
ext_long (!f ? i : j);
}
-float
+NOMIPS16 float
sub7 (float f, float g, int i)
{
ext_float (i ? f : g);
}
-float
+NOMIPS16 float
sub8 (float f, float g, long l)
{
ext_float (!l ? f : g);
}
-float
+NOMIPS16 float
sub9 (float f, float g, float h)
{
ext_float (h ? f : g);
}
-double
+NOMIPS16 double
suba (double f, double g, int i)
{
ext_double (i ? f : g);
}
-double
+NOMIPS16 double
subb (double f, double g, long l)
{
ext_double (!l ? f : g);
}
-double
+NOMIPS16 double
subc (double f, double g, double h)
{
ext_double (!h ? f : g);
/* { dg-mips-options "-O2 -march=vr5400 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmsac\t\\\$0," 2 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return z - (long long) y * x;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
long long t = (long long) x * y;
/* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return z - (long long) y * x;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
long long t = (long long) x * y;
/* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */
/* { dg-final { scan-assembler-times "\tmsub\t\\\$ac" 2 } } */
-long long
+NOMIPS16 long long
f1 (int x, int y, long long z)
{
return z - (long long) y * x;
}
-long long
+NOMIPS16 long long
f2 (int x, int y, long long z)
{
long long t = (long long) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return z - (ull) y * x;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return z - (ull) y * x;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
typedef unsigned int ui;
typedef unsigned long long ull;
-ull
+NOMIPS16 ull
f1 (ui x, ui y, ull z)
{
return z - (ull) y * x;
}
-ull
+NOMIPS16 ull
f2 (ui x, ui y, ull z)
{
ull t = (ull) x * y;
/* { dg-final { scan-assembler "nmsub.s" } } */
/* { dg-final { scan-assembler "nmsub.d" } } */
-float
+NOMIPS16 float
sub1 (float f, float g, float h)
{
return -((f * g) + h);
}
-double
+NOMIPS16 double
sub2 (double f, double g, double h)
{
return -((f * g) + h);
}
-float
+NOMIPS16 float
sub3 (float f, float g, float h)
{
return -((f * g) - h);
}
-double
+NOMIPS16 double
sub4 (double f, double g, double h)
{
return -((f * g) - h);
/* { dg-final { scan-assembler "nmsub.s" } } */
/* { dg-final { scan-assembler "nmsub.d" } } */
-float
+NOMIPS16 float
sub1 (float f, float g, float h)
{
return -((f * g) + h);
}
-double
+NOMIPS16 double
sub2 (double f, double g, double h)
{
return -((f * g) + h);
}
-float
+NOMIPS16 float
sub3 (float f, float g, float h)
{
return -((f * g) - h);
}
-double
+NOMIPS16 double
sub4 (double f, double g, double h)
{
return -((f * g) - h);
extern double sqrt(double);
extern float sqrtf(float);
-double foo(double x)
+NOMIPS16 double foo(double x)
{
return 1.0/sqrt(x);
}
-float bar(float x)
+NOMIPS16 float bar(float x)
{
return 1.0f/sqrtf(x);
}
extern double sqrt(double);
extern float sqrtf(float);
-double foo(double x)
+NOMIPS16 double foo(double x)
{
return sqrt(1.0/x);
}
-float bar(float x)
+NOMIPS16 float bar(float x)
{
return sqrtf(1.0f/x);
}
typedef float v2sf __attribute__ ((vector_size (8)));
-v2sf divide (v2sf a, v2sf b)
+NOMIPS16 v2sf divide (v2sf a, v2sf b)
{
return a / b;
}
-v2sf recip (v2sf a)
+NOMIPS16 v2sf recip (v2sf a)
{
return ((v2sf) {1.0, 1.0}) / a;
}
-v2sf squareroot (v2sf a)
+NOMIPS16 v2sf squareroot (v2sf a)
{
return __builtin_mips_sqrt_ps (a);
}
-v2sf rsqrt (v2sf a)
+NOMIPS16 v2sf rsqrt (v2sf a)
{
return ((v2sf) {1.0, 1.0}) / __builtin_mips_sqrt_ps (a);
}
is preferred over mtlo/msac. */
/* { dg-do compile } */
/* { dg-mips-options "-O2 -march=vr5400" } */
-int f1 (int a, int b, int c) { return a + b * c; }
-int f2 (int a, int b, int c) { return a - b * c; }
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
is preferred over mtlo/msac. */
/* { dg-do compile } */
/* { dg-mips-options "-O2 -march=vr5500" } */
-int f1 (int a, int b, int c) { return a + b * c; }
-int f2 (int a, int b, int c) { return a - b * c; }
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
lappend vectorizer_options "-msse2"
set test_tree_vectorize 1
} elseif { [istarget "mipsisa64*-*-*"]
- && [check_effective_target_mpaired_single] } {
+ && [check_effective_target_mpaired_single]
+ && [check_effective_target_nomips16] } {
lappend vectorizer_options "-mpaired-single"
set test_tree_vectorize 1
} elseif [istarget "sparc*-*-*"] {
}]
}
+# Return true if the target is a MIPS target that does not produce
+# MIPS16 code.
+
+proc check_effective_target_nomips16 { } {
+ return [check_no_compiler_messages nomips16 object {
+ #ifndef __mips
+ #error FOO
+ #else
+ /* A cheap way of testing for -mflip-mips16. */
+ void foo (void) { asm ("addiu $20,$20,1"); }
+ void bar (void) { asm ("addiu $20,$20,1"); }
+ #endif
+ }]
+}
+
# Add the options needed for MIPS16 function attributes. At the moment,
# we don't support MIPS16 PIC.
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