(define_function_unit "fpu" 1 0
(and (eq_attr "type" "ssqrt")
- (eq_attr "cpu" "ppc604,ppc620"))
+ (eq_attr "cpu" "ppc620"))
31 31)
(define_function_unit "fpu" 1 0
(and (eq_attr "type" "dsqrt")
- (eq_attr "cpu" "ppc604,ppc620"))
+ (eq_attr "cpu" "ppc620"))
31 31)
; RIOS2 has two symmetric FPUs.
(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
- "divw %0, %1, %2"
+ "divw %0,%1,%2"
[(set_attr "type" "idiv")])
(define_expand "udivsi3"
(udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_POWERPC"
- "divwu %0, %1, %2"
+ "divwu %0,%1,%2"
[(set_attr "type" "idiv")])
;; For powers of two we can do srai/aze for divide and then adjust for
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
- "TARGET_PPCFPX || TARGET_POWER2"
+ "TARGET_PPC_GPOPT || TARGET_POWER2"
"")
(define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GPOPT"
"fsqrts %0,%1"
[(set_attr "type" "ssqrt")])
(const_int 0))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"
{ operands[3] = gen_reg_rtx (SFmode); }")
(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "reg_or_short_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(minus:SF (match_dup 1) (match_dup 2)))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(const_int 0))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"
{ operands[3] = gen_reg_rtx (SFmode); }")
(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "reg_or_short_operand" "")))
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(minus:SF (match_dup 2) (match_dup 1)))
(set (match_operand:SF 0 "gpc_reg_operand" "")
(const_int 0))
(match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
(define_insn "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
- "TARGET_PPCFPX || TARGET_POWER2"
+ "TARGET_PPC_GPOPT || TARGET_POWER2"
"fsqrt %0,%1"
[(set_attr "type" "dsqrt")])
(const_int 0))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "reg_or_short_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(minus:DF (match_dup 1) (match_dup 2)))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(const_int 0))
(match_dup 1)
(match_dup 2)))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"
{ operands[3] = gen_reg_rtx (DFmode); }")
(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "reg_or_short_operand" "")))
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
[(set (match_dup 3)
(minus:DF (match_dup 2) (match_dup 1)))
(set (match_operand:DF 0 "gpc_reg_operand" "")
(const_int 0))
(match_operand:DF 2 "gpc_reg_operand" "f")
(match_operand:DF 3 "gpc_reg_operand" "f")))]
- "TARGET_PPCFPX"
+ "TARGET_PPC_GFXOPT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
\f
{
rs6000_trunc_used = 1;
}")
+
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
+ "TARGET_POWERPC64"
+ "fcfid %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "fix_truncdfdi2"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+ (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
+ "TARGET_POWERPC64"
+ "fctidz %0,%1"
+ [(set_attr "type" "fp")])
\f
;; Define the DImode operations that can be done in a small number
;; of instructions.
;; just handle shifts by constants.
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_scratch:SI 3 ""))])]
sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
[(set_attr "length" "8")])
\f
+;; PowerPC64 DImode operations.
+
+(define_insn "ffsdi2"
+ [(set (match_operand:DI 0 "register_operand" "=&r")
+ (ffs:DI (match_operand:DI 1 "register_operand" "r")))]
+ "TARGET_POWERPC64"
+ "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
+ [(set_attr "length" "16")])
+
+(define_insn "muldi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+ (match_operand:DI 2 "reg_or_short_operand" "r")))]
+ "TARGET_POWERPC64"
+ "mulld %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "smuldi3_highpart"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (truncate:DI
+ (lshiftrt:TI (mult:TI (sign_extend:TI
+ (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (sign_extend:TI
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 64))))]
+ "TARGET_POWERPC64"
+ "mulhd %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "umuldi3_highpart"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (truncate:DI
+ (lshiftrt:TI (mult:TI (zero_extend:TI
+ (match_operand:DI 1 "gpc_reg_operand" "%r"))
+ (zero_extend:TI
+ (match_operand:DI 2 "gpc_reg_operand" "r")))
+ (const_int 64))))]
+ "TARGET_POWERPC64"
+ "mulhdu %0,%1,%2"
+ [(set_attr "type" "imul")])
+
+(define_insn "divdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "divd %0,%1,%2"
+ [(set_attr "type" "idiv")])
+
+(define_insn "udivdi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_POWERPC64"
+ "divdu %0,%1,%2"
+ [(set_attr "type" "idiv")])
+
+(define_insn "rotldi3"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
+ "TARGET_POWERPC64"
+ "rld%I2cl %0,%1,%h2,0")
+
+(define_insn ""
+ [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+ (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (clobber (match_scratch:DI 3 "=r"))]
+ "TARGET_POWERPC64"
+ "rld%I2cl. %3,%1,%h2,0"
+ [(set_attr "type" "delayed_compare")])
+
+(define_insn ""
+ [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+ (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "reg_or_cint_operand" "ri"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (rotate:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_POWERPC64"
+ "rld%I2cl. %0,%1,%h2,0"
+ [(set_attr "type" "delayed_compare")])
+\f
;; Now define ways of moving data around.
;;
;; For SI, we special-case integers that can't be loaded in one insn. We
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DImode, operands[1]);
+
+ /* Stores between FPR and any non-FPR registers must go through a
+ temporary stack slot. */
+
+ if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+ && ((FP_REGNO_P (REGNO (operands[0]))
+ && ! FP_REGNO_P (REGNO (operands[1])))
+ || (FP_REGNO_P (REGNO (operands[1]))
+ && ! FP_REGNO_P (REGNO (operands[0])))))
+ {
+ rtx stack_slot;
+
+ if (reload_in_progress)
+ stack_slot = gen_rtx (MEM, DImode,
+ plus_constant (stack_pointer_rtx, 8));
+ else
+ stack_slot = assign_stack_temp (DImode, 8, 0);
+ emit_move_insn (stack_slot, operands[1]);
+ emit_move_insn (operands[0], stack_slot);
+ DONE;
+ }
}")
(define_insn ""
"@
doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
{ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
- [(set_attr "type" "delayed_compare,compare")
+ [(set_attr "type" "compare,delayed_compare")
(set_attr "length" "12")])
(define_insn ""