* config/m68hc11/m68hc11.md (peephole2): New peephole2 to optimize

	address computation and memory moves.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@55267 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 767dd73..a3086e1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2002-07-06  Stephane Carrez  <stcarrez@nerim.fr>
+
+       * config/m68hc11/m68hc11.md (peephole2): New peephole2 to optimize
+       address computation and memory moves.
+
 2002-07-03  Mark Mitchell  <mark@codesourcery.com>
 
        PR c++/6706

diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md
index ce32b53..7ee9ffa 100644 (file)
--- a/gcc/config/m68hc11/m68hc11.md
+++ b/gcc/config/m68hc11/m68hc11.md
@@ -6479,29 +6479,35 @@
 ;;--------------------------------------------------------------------
 
 ;;
-;; Reorganize to optimize address computations.
+;; Replace "leas 2,sp" with a "pulx" or a "puly".
+;; On 68HC12, this is one cycle slower but one byte smaller.
+;; pr target/6899: This peephole is not valid because a register CSE
+;; pass removes the pulx/puly.
 ;;
 (define_peephole2
-  [(set (match_operand:HI 0 "hard_reg_operand" "")
-       (match_operand:HI 1 "const_int_operand" ""))
-   (set (match_dup 0)
-       (plus:HI (match_dup 0)
-                (match_operand:HI 2 "general_operand" "")))]
-  "(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
-  "")
+  [(set (reg:HI SP_REGNUM) (plus:HI (reg:HI SP_REGNUM) (const_int 2)))
+   (match_scratch:HI 0 "xy")]
+  "0 && TARGET_M6812 && optimize_size"
+  [(set (match_dup 0) (match_dup 1))]
+  "operands[1] = gen_rtx (MEM, HImode,
+                         gen_rtx (POST_INC, HImode,
+                                  gen_rtx_REG (HImode, HARD_SP_REGNUM)));")
 
 ;;
-;; Reorganize address computation based on stack pointer.
+;; Optimize memory<->memory moves when the value is also loaded in
+;; a register.
 ;;
 (define_peephole2
-  [(set (match_operand:HI 0 "hard_reg_operand" "")
-        (match_operand:HI 1 "const_int_operand" ""))
-   (set (match_dup 0) (plus:HI (match_dup 0) (reg:HI SP_REGNUM)))]
-  ""
-  [(set (match_dup 0) (reg:HI SP_REGNUM))
-   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
+  [(set (match_operand:QI 0 "memory_operand" "")
+       (match_operand:QI 1 "memory_operand" ""))
+   (set (reg:QI D_REGNUM)
+       (match_operand:QI 2 "memory_operand" ""))]
+  "(rtx_equal_p (operands[0], operands[2]) && !side_effects_p (operands[0]))
+   || (GET_CODE (XEXP (operands[0], 0)) == REG
+       && GET_CODE (XEXP (operands[2], 0)) == POST_INC
+       && rtx_equal_p (XEXP (operands[0], 0), XEXP (XEXP (operands[2], 0), 0)))"
+  [(set (reg:QI D_REGNUM) (match_dup 1))
+   (set (match_dup 2) (reg:QI D_REGNUM))]
   "")
 
 ;;
@@ -6521,8 +6527,39 @@
   "")
 
 ;;
+;; Optimize loading a constant to memory when that same constant
+;; is loaded to a hard register.  Switch the two to use the register
+;; for memory initialization.  In most cases, the constant is 0.
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "memory_operand" "")
+       (match_operand:HI 1 "immediate_operand" ""))
+   (set (match_operand:HI 2 "hard_reg_operand" "")
+        (match_dup 1))]
+  "(D_REG_P (operands[2]) || X_REG_P (operands[2]) || Y_REG_P (operands[2]))
+   && !reg_mentioned_p (operands[2], operands[0])
+   && GET_MODE (operands[2]) == HImode"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (match_dup 2))]
+  "")
+
+;;
+;; Reorganize to optimize address computations.
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+       (match_operand:HI 1 "const_int_operand" ""))
+   (set (match_dup 0)
+       (plus:HI (match_dup 0)
+                (match_operand:HI 2 "general_operand" "")))]
+  "(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
+  "")
+
+;;
 ;; Optimize an address register increment and a compare to use
-;; a PRE_INC or PRE_DEC addressing mode (disabled on the compare insn
+;; a PRE_INC or PRE_DEC addressing mode (disabled on the tst insn
 ;; before reload, but can be enabled after).
 ;;
 (define_peephole2
@@ -6530,6 +6567,27 @@
        (plus:HI (match_dup 0)
                 (match_operand:HI 1 "const_int_operand" "")))
    (set (cc0)
+       (match_operand:QI 2 "memory_operand" ""))]
+  "TARGET_AUTO_INC_DEC
+   && (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1)
+   && reg_mentioned_p (operands[0], operands[2])"
+  [(set (cc0) (match_dup 3))]
+  "if (INTVAL (operands[1]) == 1)
+     operands[3] = gen_rtx (MEM, QImode,
+                           gen_rtx (PRE_INC, HImode, operands[0]));
+   else
+     operands[3] = gen_rtx (MEM, QImode,
+                           gen_rtx (PRE_DEC, HImode, operands[0]));
+  ")
+
+;;
+;; Likewise for compare.
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+       (plus:HI (match_dup 0)
+                (match_operand:HI 1 "const_int_operand" "")))
+   (set (cc0)
        (compare (match_operand:QI 2 "hard_reg_operand" "")
                 (match_operand:QI 3 "memory_operand" "")))]
   "TARGET_AUTO_INC_DEC
@@ -6564,6 +6622,47 @@
   ")
 
 ;;
+;; Replace a "ldx #N; addx <sp>" with a "ldx <sp>; addx #n"
+;; (avoids many temporary moves because we can't add sp to another reg easily)
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+        (match_operand:HI 1 "const_int_operand" ""))
+   (set (match_dup 0) (plus:HI (match_dup 0) (reg:HI SP_REGNUM)))]
+  ""
+  [(set (match_dup 0) (reg:HI SP_REGNUM))
+   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
+  "")
+
+;;
+;; Replace "ldd #N; addd <op>" with "ldd <op>; addd #N".
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+       (match_operand:HI 1 "const_int_operand" ""))
+   (set (match_dup 0)
+       (plus:HI (match_dup 0)
+                (match_operand:HI 2 "general_operand" "")))]
+  "(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
+  "")
+
+;;
+;; Replace a "ldd <mem>; psha; pshb" with a "ldx <mem>; pshx".
+;;
+(define_peephole2
+  [(set (match_operand:HI 0 "hard_reg_operand" "")
+        (match_operand:HI 1 "memory_operand" ""))
+   (set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
+        (match_dup 0))
+   (match_scratch:HI 2 "x")]
+  "TARGET_M6811 && D_REG_P (operands[0]) && peep2_reg_dead_p (2, operands[0])"
+  [(set (match_dup 2) (match_dup 1))
+   (set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))]
+  "")
+
+;;
 ;; This peephole catches the address computations generated by the reload
 ;; pass. 
 (define_peephole