* pa.md (floatunssisf2, floatunssidf2): Generate different RTL

        for TARGET_PA_20.
        (floatunssidf2_pa20, floatunssisf2_pa20): New patterns for PA2.0
        code generation.
        (floatunsdisf2, floatunsdidf2, fixuns_truncsfsi2): Likewise.
        (fixuns_truncdfsi2, fixuns_truncsfdi2, fixuns_truncdfsi2): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@29595 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2bb3da4..71ae5ed 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -37,6 +37,13 @@ Wed Sep 22 06:25:15 1999  Jim Kingdon  <http://developer.redhat.com>
 
 Wed Sep 22 06:06:57 1999  Jeffrey A Law  (law@cygnus.com)
 
+       * pa.md (floatunssisf2, floatunssidf2): Generate different RTL
+       for TARGET_PA_20.
+       (floatunssidf2_pa20, floatunssisf2_pa20): New patterns for PA2.0
+       code generation.
+       (floatunsdisf2, floatunsdidf2, fixuns_truncsfsi2): Likewise.
+       (fixuns_truncdfsi2, fixuns_truncsfdi2, fixuns_truncdfsi2): Likewise.
+
        * regclass.c (init_regs): Add "top_of_stack" as a garbage
        collection root.
 

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index eff818b..c6acda9 100644 (file)
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2860,7 +2860,15 @@
    (set (match_operand:SF 0 "register_operand" "")
        (float:SF (match_dup 2)))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
-  "operands[2] = gen_reg_rtx (DImode);")
+  "
+{
+  if (TARGET_PA_20)
+    {
+      emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
+      DONE;
+    }
+  operands[2] = gen_reg_rtx (DImode);
+}")
 
 (define_expand "floatunssidf2"
   [(set (subreg:SI (match_dup 2) 1)
@@ -2870,7 +2878,15 @@
    (set (match_operand:DF 0 "register_operand" "")
        (float:DF (match_dup 2)))]
   "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
-  "operands[2] = gen_reg_rtx (DImode);")
+  "
+{
+  if (TARGET_PA_20)
+    {
+      emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
+      DONE;
+    }
+  operands[2] = gen_reg_rtx (DImode);
+}")
 
 (define_insn "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -2922,6 +2938,70 @@
   "fcnvfxt,dbl,dbl %1,%0"
   [(set_attr "type" "fpalu")
    (set_attr "length" "4")])
+
+(define_insn "floatunssidf2_pa20"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,uw,dbl %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "floatunssisf2_pa20"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,uw,sgl %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "floatunsdisf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+       (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,udw,sgl %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "floatunsdidf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+       (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,udw,dbl %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "fixuns_truncsfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,t,sgl,uw %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "fixuns_truncdfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,t,dbl,uw %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "fixuns_truncsfdi2"
+  [(set (match_operand:DI 0 "register_operand" "=f")
+       (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,t,sgl,udw %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
+
+(define_insn "fixuns_truncdfdi2"
+  [(set (match_operand:DI 0 "register_operand" "=f")
+       (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
+  "! TARGET_SOFT_FLOAT && TARGET_PA_20"
+  "fcnv,t,dbl,udw %1,%0"
+  [(set_attr "type" "fpalu")
+   (set_attr "length" "4")])
 \f
 ;;- arithmetic instructions