gcc/

2010-09-21  Mingming Sun  <mingm.sun@gmail.com>

	* doc/invoke.texi (MIPS Options): Add loongson3a processor.
	* config/mips/mips.md (define_attr "cpu"): Add loongson_3a.
	(define_insn "prefetch"): Add TARGET_LOONGSON_3A.
	* config/mips/mips.h (TARGET_LOONGSON_3A): Define.
	(TUNE_LOONGSON_3A): Define.
	(TARGET_LOONGSON_VECTORS): Add TARGET_LOONGSON_3A.
	(MIPS_ISA_LEVEL_SPEC): Add loongson3a.
	* config/mips/mips.c (mips_cpu_info_table): Add loongson3a.
	(mips_issue_rate): Add PROCESSOR_LOONGSON_3A.
	(mips_rtx_cost_data): Add Loongson-3A.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@166716 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4c07f72..08dd481 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2010-11-13  Mingming Sun  <mingm.sun@gmail.com>
+
+       * doc/invoke.texi (MIPS Options): Add loongson3a processor.
+       * config/mips/mips.md (define_attr "cpu"): Add loongson_3a.
+       (define_insn "prefetch"): Add TARGET_LOONGSON_3A.
+       * config/mips/mips.h (TARGET_LOONGSON_3A): Define.
+       (TUNE_LOONGSON_3A): Define.
+       (TARGET_LOONGSON_VECTORS): Add TARGET_LOONGSON_3A.
+       (MIPS_ISA_LEVEL_SPEC): Add loongson3a.
+       * config/mips/mips.c (mips_cpu_info_table): Add loongson3a.
+       (mips_issue_rate): Add PROCESSOR_LOONGSON_3A.
+       (mips_rtx_cost_data): Add Loongson-3A.
+
 2010-11-13  Iain Sandoe  <iains@gcc.gnu.org>
 
        * config/darwin.h (LINK_COMMAND_SPEC_A): Update for changes to lto

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 76c0786..de587a5 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -779,6 +779,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
   { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
   { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
   { "xlr", PROCESSOR_XLR, 64, 0 },
+  { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
 
   /* MIPS64 Release 2 processors.  */
   { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
@@ -979,6 +980,9 @@ static const struct mips_rtx_cost_data
   { /* Loongson-2F */
     DEFAULT_COSTS
   },
+  { /* Loongson-3A */
+    DEFAULT_COSTS
+  },
   { /* M4k */
     DEFAULT_COSTS
   },
@@ -12040,6 +12044,7 @@ mips_issue_rate (void)
 
     case PROCESSOR_LOONGSON_2E:
     case PROCESSOR_LOONGSON_2F:
+    case PROCESSOR_LOONGSON_3A:
       return 4;
 
     default:

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7b5e140..392e457 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -218,6 +218,7 @@ enum mips_code_readable_setting {
 #define TARGET_LOONGSON_2E          (mips_arch == PROCESSOR_LOONGSON_2E)
 #define TARGET_LOONGSON_2F          (mips_arch == PROCESSOR_LOONGSON_2F)
 #define TARGET_LOONGSON_2EF         (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
+#define TARGET_LOONGSON_3A          (mips_arch == PROCESSOR_LOONGSON_3A)
 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
 #define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
 #define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)
@@ -242,6 +243,7 @@ enum mips_code_readable_setting {
                                     || mips_tune == PROCESSOR_74KF3_2)
 #define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E        \
                                     || mips_tune == PROCESSOR_LOONGSON_2F)
+#define TUNE_LOONGSON_3A            (mips_tune == PROCESSOR_LOONGSON_3A)
 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
@@ -261,7 +263,8 @@ enum mips_code_readable_setting {
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
    floating-point registers provide 64-bit values.  */
 #define TARGET_LOONGSON_VECTORS            (TARGET_HARD_FLOAT_ABI              \
-                                    && TARGET_LOONGSON_2EF)
+                                    && (TARGET_LOONGSON_2EF            \
+                                        || TARGET_LOONGSON_3A))
 
 /* True if the pre-reload scheduler should try to create chains of
    multiply-add or multiply-subtract instructions.  For example,
@@ -716,7 +719,7 @@ enum mips_code_readable_setting {
      %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
        |march=34k*|march=74k*|march=1004k*: -mips32r2} \
      %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
-       |march=xlr: -mips64} \
+       |march=xlr|march=loongson3a: -mips64} \
      %{march=mips64r2|march=octeon: -mips64r2} \
      %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
 

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index b789394..2f9b779 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -39,6 +39,7 @@
   74kf3_2
   loongson_2e
   loongson_2f
+  loongson_3a
   m4k
   octeon
   r3900
@@ -6247,8 +6248,8 @@
             (match_operand 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
 {
-  if (TARGET_LOONGSON_2EF)
-    /* Loongson 2[ef] use load to $0 to perform prefetching.  */
+  if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
+    /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching.  */
     return "ld\t$0,%a0";
   operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
   return "pref\t%1,%a0";

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 51a110e..103aa78 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -14035,7 +14035,7 @@ The processor names are:
 @samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1},
 @samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
 @samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
-@samp{loongson2e}, @samp{loongson2f},
+@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
 @samp{m4k},
 @samp{octeon},
 @samp{orion},