gcc/

	* config/mips/mips.md: Use match_test rather than eq/ne symbol_ref
	throughout file.
	* config/mips/sb1.md: Likewise.
	* config/mips/predicates.md: Replace (match_test "!...")
	with (not (match_test "..."))
	* config/mips/constraints.md: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178759 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce7c22c..415c19f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2011-09-11  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/mips/mips.md: Use match_test rather than eq/ne symbol_ref
+       throughout file.
+       * config/mips/sb1.md: Likewise.
+       * config/mips/predicates.md: Replace (match_test "!...")
+       with (not (match_test "..."))
+       * config/mips/constraints.md: Likewise.
+
 2011-09-09  Andrew Stubbs  <ams@codesourcery.com>
 
        * config/arm/arm-cores.def (generic-armv7-a): New architecture.

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index 37eee87..2bfb2aa 100644 (file)
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -127,9 +127,9 @@
   "A constant that cannot be loaded using @code{lui}, @code{addiu}
    or @code{ori}."
   (and (match_code "const_int")
-       (match_test "!SMALL_OPERAND (ival)")
-       (match_test "!SMALL_OPERAND_UNSIGNED (ival)")
-       (match_test "!LUI_OPERAND (ival)")))
+       (not (match_test "SMALL_OPERAND (ival)"))
+       (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
+       (not (match_test "LUI_OPERAND (ival)"))))
 
 (define_constraint "N"
   "A constant in the range -65535 to -1 (inclusive)."
@@ -184,7 +184,7 @@
    using @code{la}."
   (and (match_operand 0 "move_operand")
        (match_test "CONSTANT_P (op)")
-       (match_test "!mips_dangerous_for_la25_p (op)")))
+       (not (match_test "mips_dangerous_for_la25_p (op)"))))
 
 (define_memory_constraint "W"
   "@internal
@@ -194,7 +194,7 @@
    constant-pool references."
   (and (match_code "mem")
        (match_operand 0 "memory_operand")
-       (ior (match_test "!TARGET_MIPS16")
+       (ior (not (match_test "TARGET_MIPS16"))
            (and (not (match_operand 0 "stack_operand"))
                 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
 

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index de95321..c2211a3 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -210,11 +210,11 @@
 ;; True if the main data type is twice the size of a word.
 (define_attr "dword_mode" "no,yes"
   (cond [(and (eq_attr "mode" "DI,DF")
-             (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
+             (not (match_test "TARGET_64BIT")))
         (const_string "yes")
 
         (and (eq_attr "mode" "TI,TF")
-             (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
+             (match_test "TARGET_64BIT"))
         (const_string "yes")]
        (const_string "no")))
 
@@ -384,7 +384,7 @@
 ;; Length of instruction in bytes.
 (define_attr "length" ""
    (cond [(and (eq_attr "extended_mips16" "yes")
-              (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
+              (match_test "TARGET_MIPS16"))
          (const_int 8)
 
          ;; Direct branch instructions have a range of [-0x20000,0x1fffc],
@@ -423,7 +423,7 @@
                   (const_int 4)
 
                 ;; The non-PIC case: branch, first delay slot, and J.
-                (ne (symbol_ref "TARGET_ABSOLUTE_JUMPS") (const_int 0))
+                (match_test "TARGET_ABSOLUTE_JUMPS")
                   (const_int 12)]
 
                 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
@@ -439,7 +439,7 @@
          (const_int 0)
 
          (eq_attr "got" "load")
-         (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+         (if_then_else (match_test "TARGET_MIPS16")
                        (const_int 8)
                        (const_int 4))
          (eq_attr "got" "xgot_high")
@@ -456,7 +456,7 @@
          ;; SHIFT_SHIFTs are decomposed into two separate instructions.
          ;; They are extended instructions on MIPS16 targets.
          (eq_attr "move_type" "shift_shift")
-         (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+         (if_then_else (match_test "TARGET_MIPS16")
                        (const_int 16)
                        (const_int 8))
 
@@ -479,7 +479,7 @@
          (eq_attr "move_type" "load,fpload")
          (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
          (eq_attr "move_type" "store,fpstore")
-         (cond [(eq (symbol_ref "TARGET_FIX_24K") (const_int 0))
+         (cond [(not (match_test "TARGET_FIX_24K"))
                 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]
                 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))
 
@@ -500,7 +500,7 @@
          ;; instruction.  The assembler does this for us, so account for
          ;; the worst-case length here.
          (and (eq_attr "type" "imadd")
-              (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
+              (match_test "TARGET_FIX_VR4120"))
          (const_int 8)
 
          ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
@@ -508,7 +508,7 @@
          ;; around this by inserting a nop after the first dmult.
          (and (eq_attr "type" "imul,imul3")
               (and (eq_attr "mode" "DI")
-                   (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
+                   (match_test "TARGET_FIX_VR4120")))
          (const_int 8)
 
          (eq_attr "type" "idiv,idiv3")
@@ -528,24 +528,24 @@
 ;; write to HI or LO.
 (define_attr "hazard" "none,delay,hilo"
   (cond [(and (eq_attr "type" "load,fpload,fpidxload")
-             (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
+             (match_test "ISA_HAS_LOAD_DELAY"))
         (const_string "delay")
 
         (and (eq_attr "type" "mfc,mtc")
-             (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
+             (match_test "ISA_HAS_XFER_DELAY"))
         (const_string "delay")
 
         (and (eq_attr "type" "fcmp")
-             (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
+             (match_test "ISA_HAS_FCMP_DELAY"))
         (const_string "delay")
 
         ;; The r4000 multiplication patterns include an mflo instruction.
         (and (eq_attr "type" "imul")
-             (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
+             (match_test "TARGET_FIX_R4000"))
         (const_string "hilo")
 
         (and (eq_attr "type" "mfhilo")
-             (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
+             (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
         (const_string "hilo")]
        (const_string "none")))
 
@@ -565,7 +565,7 @@
 ;; Attribute defining whether or not we can use the branch-likely
 ;; instructions.
 (define_attr "branch_likely" "no,yes"
-  (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+  (if_then_else (match_test "GENERATE_BRANCHLIKELY")
                (const_string "yes")
                (const_string "no")))
 
@@ -849,7 +849,7 @@
 ;; .........................
 
 (define_delay (and (eq_attr "type" "branch")
-                  (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+                  (not (match_test "TARGET_MIPS16"))
                   (eq_attr "branch_likely" "yes"))
   [(eq_attr "can_delay" "yes")
    (nil)
@@ -857,7 +857,7 @@
 
 ;; Branches that don't have likely variants do not annul on false.
 (define_delay (and (eq_attr "type" "branch")
-                  (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+                  (not (match_test "TARGET_MIPS16"))
                   (eq_attr "branch_likely" "no"))
   [(eq_attr "can_delay" "yes")
    (nil)
@@ -1783,7 +1783,7 @@
   [(set_attr "type" "imul")
    (set_attr "mode" "SI")
    (set (attr "length")
-       (if_then_else (ne (symbol_ref "ISA_HAS_EXT_INS") (const_int 0))
+       (if_then_else (match_test "ISA_HAS_EXT_INS")
                      (const_int 16)
                      (const_int 28)))])
 
@@ -2287,7 +2287,7 @@
   [(set_attr "type" "fdiv")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length")
-        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+        (if_then_else (match_test "TARGET_FIX_SB1")
                       (const_int 8)
                       (const_int 4)))])
 
@@ -2305,7 +2305,7 @@
   [(set_attr "type" "frdiv")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length")
-        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+        (if_then_else (match_test "TARGET_FIX_SB1")
                       (const_int 8)
                       (const_int 4)))])
 
@@ -2409,7 +2409,7 @@
   [(set_attr "type" "fsqrt")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length")
-        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+        (if_then_else (match_test "TARGET_FIX_SB1")
                       (const_int 8)
                       (const_int 4)))])
 
@@ -2427,7 +2427,7 @@
   [(set_attr "type" "frsqrt")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length")
-        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+        (if_then_else (match_test "TARGET_FIX_SB1")
                       (const_int 8)
                       (const_int 4)))])
 
@@ -2445,7 +2445,7 @@
   [(set_attr "type" "frsqrt")
    (set_attr "mode" "<UNITMODE>")
    (set (attr "length")
-        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+        (if_then_else (match_test "TARGET_FIX_SB1")
                       (const_int 8)
                       (const_int 4)))])
 \f

diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md
index 022868b..dd51480 100644 (file)
--- a/gcc/config/mips/predicates.md
+++ b/gcc/config/mips/predicates.md
@@ -59,7 +59,7 @@
 
 (define_predicate "reg_or_0_operand"
   (ior (and (match_operand 0 "const_0_operand")
-           (match_test "!TARGET_MIPS16"))
+           (not (match_test "TARGET_MIPS16")))
        (match_operand 0 "register_operand")))
 
 (define_predicate "const_1_operand"
@@ -100,7 +100,7 @@
 
 (define_predicate "and_reg_operand"
   (ior (match_operand 0 "register_operand")
-       (and (match_test "!TARGET_MIPS16")
+       (and (not (match_test "TARGET_MIPS16"))
            (match_operand 0 "const_uns_arith_operand"))
        (match_operand 0 "low_bitmask_operand")
        (match_operand 0 "si_mask_operand")))
@@ -335,7 +335,7 @@
 
 (define_predicate "mips_cstore_operator"
   (ior (match_code "eq,gt,gtu,ge,geu,lt,ltu,le,leu")
-       (and (match_code "ne") (match_test "!TARGET_MIPS16"))))
+       (and (match_code "ne") (not (match_test "TARGET_MIPS16")))))
 
 (define_predicate "small_data_pattern"
   (and (match_code "set,parallel,unspec,unspec_volatile,prefetch")

diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md
index 8c0b760..2d36c22 100644 (file)
--- a/gcc/config/mips/sb1.md
+++ b/gcc/config/mips/sb1.md
@@ -76,8 +76,8 @@
 ;; disabled.
 
 (define_attr "sb1_fp_pipes" "one,two"
-  (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0))
-             (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0)))
+  (cond [(and (match_test "TARGET_FLOAT64")
+             (not (match_test "TARGET_FP_EXCEPTIONS")))
         (const_string "two")]
        (const_string "one")))
 
@@ -149,15 +149,13 @@
 (define_insn_reservation "ir_sb1_fpload" 0
   (and (eq_attr "cpu" "sb1,sb1a")
        (and (eq_attr "type" "fpload")
-           (ne (symbol_ref "TARGET_FLOAT64")
-               (const_int 0))))
+           (match_test "TARGET_FLOAT64")))
   "sb1_ls0 | sb1_ls1")
 
 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1
   (and (eq_attr "cpu" "sb1,sb1a")
        (and (eq_attr "type" "fpload")
-           (eq (symbol_ref "TARGET_FLOAT64")
-               (const_int 0))))
+           (not (match_test "TARGET_FLOAT64"))))
   "sb1_ls0 | sb1_ls1")
 
 ;; Indexed loads can only execute on LS1 pipe.
@@ -165,15 +163,13 @@
 (define_insn_reservation "ir_sb1_fpidxload" 0
   (and (eq_attr "cpu" "sb1,sb1a")
        (and (eq_attr "type" "fpidxload")
-           (ne (symbol_ref "TARGET_FLOAT64")
-               (const_int 0))))
+           (match_test "TARGET_FLOAT64")))
   "sb1_ls1")
 
 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
   (and (eq_attr "cpu" "sb1,sb1a")
        (and (eq_attr "type" "fpidxload")
-           (eq (symbol_ref "TARGET_FLOAT64")
-               (const_int 0))))
+           (not (match_test "TARGET_FLOAT64"))))
   "sb1_ls1")
 
 ;; prefx can only execute on the ls1 pipe.