* doc/md.texi (Machine Constraints): Correct formatting in PDP-11

constraints.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@166346 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d922771..84ff304 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2010-11-04  Paul Koning  <ni1d@arrl.net>
+
+       * doc/md.texi (Machine Constraints): Correct formatting in PDP-11
+       constraints. 
+       
 2010-11-04  Chao-ying Fu  <fu@mips.com>
 
        * configure.ac: Test assembler support for DSP Rev1 mult.

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index c9eb053..bdf42f1 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2928,8 +2928,8 @@ Floating point registers AC0 through AC3.  These can be loaded from/to
 memory with a single instruction.
 
 @item d
-Odd numbered general registers (R1, R3, R5).  These are used for 16
-bit multiply operations.
+Odd numbered general registers (R1, R3, R5).  These are used for
+16-bit multiply operations.
 
 @item f
 Any of the floating point registers (AC0 through AC5).
@@ -2951,13 +2951,13 @@ An integer constant that does not meet the constraints for codes
 The integer constant 1.
 
 @item M
-The integer constant -1.
+The integer constant @minus{}1.
 
 @item N
 The integer constant 0.
 
 @item O
-Integer constants -4 through -1 and 1 through 4; shifts by these
+Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
 amounts are handled as multiple single-bit shifts rather than a single
 variable-length shift.