* system.h: Poison SLOW_ZERO_EXTEND.
* doc/tm.texi: Remove.
* config/1750a/1750a.h (SLOW_ZERO_EXTEND): Remove.
* config/arm/arm.h: Likewise.
* config/avr/avr.h: Likewise.
* config/clipper/clipper.h: Likewise.
* config/convex/convex.h: Likewise.
* config/d30v/d30v.h: Likewise.
* config/dsp16xx/dsp16xx.h: Likewise.
* config/elxsi/elxsi.h: Likewise.
* config/fr30/fr30.h: Likewise.
* config/h8300/h8300.h: Likewise.
* config/i370/i370.h: Likewise.
* config/i386/i386.h: Likewise.
* config/m68k/m68k.h: Likewise.
* config/mips/mips.h: Likewise.
* config/ns32k/ns32k.h: Likewise.
* config/pdp11/pdp11.h: Likewise.
* config/pj/pj.h: Likewise.
* config/s390/s390.h: Likewise.
* config/sh/sh.h: Likewise.
* config/stormy16/stormy16.h: Likewise.
* config/v850/v850.h: Likewise.
* config/vax/vax.h: Likewise.
* config/we32k/we32k.h: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@48893
138bc75d-0d04-0410-961f-
82ee72b054a4
+2002-01-15 Kazu Hirata <kazu@hxi.com>
+
+ * expmed.c (extract_fixed_bit_field): Remove unused code.
+ * system.h: Poison SLOW_ZERO_EXTEND.
+ * doc/tm.texi: Remove.
+ * config/1750a/1750a.h (SLOW_ZERO_EXTEND): Remove.
+ * config/arm/arm.h: Likewise.
+ * config/avr/avr.h: Likewise.
+ * config/clipper/clipper.h: Likewise.
+ * config/convex/convex.h: Likewise.
+ * config/d30v/d30v.h: Likewise.
+ * config/dsp16xx/dsp16xx.h: Likewise.
+ * config/elxsi/elxsi.h: Likewise.
+ * config/fr30/fr30.h: Likewise.
+ * config/h8300/h8300.h: Likewise.
+ * config/i370/i370.h: Likewise.
+ * config/i386/i386.h: Likewise.
+ * config/m68k/m68k.h: Likewise.
+ * config/mips/mips.h: Likewise.
+ * config/ns32k/ns32k.h: Likewise.
+ * config/pdp11/pdp11.h: Likewise.
+ * config/pj/pj.h: Likewise.
+ * config/s390/s390.h: Likewise.
+ * config/sh/sh.h: Likewise.
+ * config/stormy16/stormy16.h: Likewise.
+ * config/v850/v850.h: Likewise.
+ * config/vax/vax.h: Likewise.
+ * config/we32k/we32k.h: Likewise.
+
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.
move-instruction pairs, we will do a movstr or libcall instead. */
#define MOVE_RATIO 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
-/* Define this if zero-extension is slow (more than one real instruction).
- On the ARM, it is more than one instruction only if not fetching from
- memory. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
subsequent accesses occur to other fields in the same word of the
structure, but to different bytes.
- `SLOW_ZERO_EXTEND'
- Define this macro if zero-extension (of a `char' or `short' to an
- `int') can be done faster if the destination is a register that is
- known to be zero.
-
- If you define this macro, you must have instruction patterns that
- recognize RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'.
-
`SLOW_UNALIGNED_ACCESS'
Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
#define MOVE_RATIO 20
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS (! TARGET_C2)
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.
loads. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a char or short to an int) can
- be done faster if the destination is a register that is know to be zero. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Define this macro if unaligned accesses have a cost many times greater than
aligned accesses, for example if they are emulated in a trap handler */
/* define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) */
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/*}}}*/ \f
/*{{{ Dividing the output into sections. */
#define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MAX_MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS TARGET_SLOWBYTE
#define MOVE_MAX 256
-/* Define this if zero-extension is slow (more than one real instruction). */
-
-#define SLOW_ZERO_EXTEND 1
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1
/* Nonzero if access to memory by shorts is slow and undesirable. */
#define SLOW_SHORT_ACCESS 0
-/* Define this macro if zero-extension (of a `char' or `short' to an
- `int') can be done faster if the destination is a register that is
- known to be zero.
-
- If you define this macro, you must have instruction patterns that
- recognize RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-
-/* #define SLOW_ZERO_EXTEND */
-
/* Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
are emulated in a trap handler.
in one reasonably fast instruction. */
#define MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
#define STORE_FLAG_VALUE 1
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
#define SHIFT_COUNT_TRUNCATED 1
We have a smart movstrsi insn */
#define MOVE_RATIO 0
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
#define MOVE_MAX 2
-/* Zero extension is faster if the target is known to be zero */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by byte is slow and undesirable. -
*/
#define SLOW_BYTE_ACCESS 0
#define SHORT_IMMEDIATES_SIGN_EXTEND
-/* Define this if zero-extension is slow (more than one real
- instruction). */
-
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1
#define MOVE_MAX 256
-/* Define this if zero-extension is slow (more than one real instruction). */
-
-#define SLOW_ZERO_EXTEND
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
-/* Define this if zero-extension is slow (more than one real instruction).
- On the SH, it's only one instruction. */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 0
-/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
- be done faster if the destination is a register that is known to be zero.
-
- If you define this macro, you must have instruction patterns that recognize
- RTL structures like this:
-
- (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
-
- and likewise for `HImode'. */
-#define SLOW_ZERO_EXTEND 0
-
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.
than accessing full words. */
#define SLOW_BYTE_ACCESS 1
-/* Define this if zero-extension is slow (more than one real instruction). */
-#define SLOW_ZERO_EXTEND
-
/* According expr.c, a value of around 6 should minimize code size, and
for the V850 series, that's our primary concern. */
#define MOVE_RATIO 6
in one reasonably fast instruction. */
#define MOVE_MAX 8
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
in one reasonably fast instruction. */
#define MOVE_MAX 4
-/* Define this if zero-extension is slow (more than one real instruction). */
-/* #define SLOW_ZERO_EXTEND */
-
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0
may eliminate subsequent memory access if subsequent accesses occur to
other fields in the same word of the structure, but to different bytes.
-@findex SLOW_ZERO_EXTEND
-@item SLOW_ZERO_EXTEND
-Define this macro if zero-extension (of a @code{char} or @code{short}
-to an @code{int}) can be done faster if the destination is a register
-that is known to be zero.
-
-If you define this macro, you must have instruction patterns that
-recognize RTL structures like this:
-
-@smallexample
-(set (strict_low_part (subreg:QI (reg:SI @dots{}) 0)) @dots{})
-@end smallexample
-
-@noindent
-and likewise for @code{HImode}.
-
@findex SLOW_UNALIGNED_ACCESS
@item SLOW_UNALIGNED_ACCESS (@var{mode}, @var{alignment})
Define this macro to be the value 1 if memory accesses described by the
/* Unless the msb of the field used to be the msb when we shifted,
mask out the upper bits. */
- if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
-#if 0
-#ifdef SLOW_ZERO_EXTEND
- /* Always generate an `and' if
- we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
- will combine fruitfully with the zero-extend. */
- || tmode != mode
-#endif
-#endif
- )
+ if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
return expand_binop (GET_MODE (op0), and_optab, op0,
mask_rtx (GET_MODE (op0), 0, bitsize, 0),
target, 1, OPTAB_LIB_WIDEN);
DOESNT_NEED_UNWINDER EH_TABLE_LOOKUP OBJC_SELECTORS_WITHOUT_LABELS \
OMIT_EH_TABLE EASY_DIV_EXPR IMPLICIT_FIX_EXPR \
LONGJMP_RESTORE_FROM_STACK MAX_INT_TYPE_SIZE ASM_IDENTIFY_GCC \
- STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE
+ STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE \
+ SLOW_ZERO_EXTEND
#endif /* IN_GCC */
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