(tstdi): Rewrite.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@9913 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index e16004e..db632e6 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -281,31 +281,26 @@
 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
 ;; be folded while optimizing anyway.
 
-(define_insn "tstdi"
+(define_expand "tstdi"
+  [(parallel
+    [(set (cc0)
+         (match_operand:DI 0 "nonimmediate_operand" "d"))
+   (clobber (match_dup 1))])]
+  ""
+  "
+{
+  operands[1] = gen_reg_rtx (DImode);
+}")
+
+(define_insn ""
   [(set (cc0)
-       (match_operand:DI 0 "nonimmediate_operand" "oa>,d"))
-   (clobber (match_scratch:SI 1 "=d,d"))
-   (clobber (match_scratch:SI 2 "=d,"))]
+       (match_operand:DI 1 "nonimmediate_operand" "0"))
+   (clobber (match_operand:DI 0 "register_operand" "=d"))]
   ""
   "*
 {
-  if (GET_CODE (operands[0]) == REG)
-    operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  else if (GET_CODE (operands[0]) == MEM
-          && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
-    operands[3] = operands[0];
-  else
-    operands[3] = adj_offsettable_operand (operands[0], 4);
-  if (DATA_REG_P (operands[0]))
-    operands[2] = operands[0];
-  else
-    output_asm_insn (\"move%.l %0,%2\", operands);
-  /*
-  ** 'sub' clears %1, and also clears the X cc bit
-  ** 'tst' sets the Z cc bit according to the low part of the DImode operand
-  ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
-  */
-  return \"sub%.l %1,%1\;tst%.l %3\;subx%.l %1,%2\";
+  cc_status.flags |= CC_REVERSED;
+  return \"neg%.l %R0\;negx%.l %0\";
 }")
 
 (define_insn "tstsi"