OSDN Git Service

2002-04-09 Eric Christopher <echristo@redhat.com>
authorechristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 10 Apr 2002 03:40:00 +0000 (03:40 +0000)
committerechristo <echristo@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 10 Apr 2002 03:40:00 +0000 (03:40 +0000)
* config/mips/mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional
information to .comm directive.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@52109 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/mips/mips.h

index e1b2ac9..fb618b4 100644 (file)
@@ -1,3 +1,8 @@
+2002-04-09  Eric Christopher  <echristo@redhat.com>
+
+       * config/mips/mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional
+       information to .comm directive.
+
 2002-04-09  Richard Henderson  <rth@redhat.com>
 
        PR c/5078
@@ -886,7 +891,7 @@ Sun Mar 31 14:43:24 2002  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
        * gcc.c (LIBGCC_SPEC): Folded %L and duplicate %G here...
        (LINK_COMMAND_SPEC): ... from here.
-       (init_gcc_specs): Duplicate it here too, omitting 
+       (init_gcc_specs): Duplicate it here too, omitting
        shared_name in the second copy.
        (init_spec): Test for duplicate
        * config/i386/djgpp.h (LINK_COMMAND_SPEC): Remove `%L %G'.
@@ -926,7 +931,7 @@ Sun Mar 31 14:43:24 2002  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
        * dwarf2out.c (dwarf2out_define): Remove start_source_file call,
        CPP will start the file for us.
+
 2002-03-30  Richard Henderson  <rth@redhat.com>
 
        PR target/5446
@@ -1296,7 +1301,7 @@ objc:
        * gcc-common.c (lang_mark_false_label_stack): Remove.
        * ggc.h (lang_mark_false_label_stack): Similarly.
 
-2002-03-26  Vladimir Makarov  <vmakarov@redhat.com> 
+2002-03-26  Vladimir Makarov  <vmakarov@redhat.com>
 
        * pa/pa-pro-end.h (CPP_PREDEFINES): Add -D__pro__.
 
@@ -1380,7 +1385,7 @@ objc:
        * stmt.c (expand_end_case_type): When warn_switch_enum /
        -Wswitch-enum, perform switch checks.
        Fix PR c/5044.
-       
+
 2002-03-26  Richard Earnshaw  <rearnsha@arm.com>
 
        * arm.md (reload_mulsi3, reload_mulsi_compare0, reload_muladdsi)
@@ -1406,7 +1411,7 @@ objc:
 2002-03-26  Hartmut Penner  <hpenner@de.ibm.com>
 
        * config/s390/s390.c (s390_emit_epilogue): Change epilogue
-       code to not restoring global registers. 
+       code to not restoring global registers.
 
 2002-03-26  Neil Booth  <neil@daikokuya.demon.co.uk>
 
index 976f0b7..6db24f4 100644 (file)
@@ -2311,7 +2311,7 @@ extern enum reg_class mips_char_to_class[256];
    memory and loading that memory location into a register of CLASS2.
 
    Do not define this macro if its value would always be zero.  */
-
+#if 0
 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)                  \
   ((!TARGET_DEBUG_H_MODE                                               \
     && GET_MODE_CLASS (MODE) == MODE_INT                               \
@@ -2320,7 +2320,7 @@ extern enum reg_class mips_char_to_class[256];
    || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode             \
        && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS)              \
           || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
-
+#endif
 /* The HI and LO registers can only be reloaded via the general
    registers.  Condition code registers can only be loaded to the
    general registers, and from the floating point registers.  */
@@ -4485,8 +4485,11 @@ while (0)
            (SIZE));                                                    \
       }                                                                        \
     else                                                               \
-      mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n",       \
+      {                                                                        \
+       mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u",        \
          (SIZE));                                                      \
+       fprintf ((STREAM), "%u\n", ((unsigned)(ALIGN) / BITS_PER_UNIT));\
+      }                                                                        \
   } while (0)