* h8300/h8300.h (FIRST_PSEUDO_REGISTER): Bump up by one.

        (ARG_POINTER_REGNUM): Likewise.
        (FIXED_REGISTERS): Add entry for MAC register.
        (CALL_USED_REGISTERS< REG_ALLOC_ORDER): Likewise.
        (HARD_REGNO_NREGS): Handle MAC register.
        (HARD_REGNO_MODE_OK< REGNO_OK_FOR_BASE_P): LIkewise.
        (REGISTER_NAMES): Likewise.
        (enum reg_class): New MAC_REGS register class.
        (REG_CLASS_CONTENTS, REGNO_REG_CLASS): Corresponding changes.
        (REG_CLASS_FROM_LETTER): LIkewise.
        (REGISTER_MOVE_COST): Make copies to/from the MAC register
        expenseive.
        (CONDITIONAL_REGISTER_USAGE): Define.
        * h8300/h8300.md (movsi_h8300hs): Renamed from movsi_h8300h.
        Handle moves to/from the MAC register.
        (mac): Two new patterns to use the mac instruction.

        * h8300/h8300.c (notice_update_cc): Fix CC_SET case.
        (restore_compare_p): Remove unused function.
        * h8300/h8300.md: Handle "set" vs "set_zn_c0" correctly.
        (bCC patterns): No longer need to call restore_compare_p.

        * h8300/h8300.c (get_shift_alg): Fix HImode ASHIFTRT by
        13 or 14 bits.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@12848 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 0f1d1d7..440b219 100644 (file)
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -1574,11 +1574,10 @@ notice_update_cc (body, insn)
       break;
 
     case CC_SET:
-      /* Insn sets the Z,N flags of CC to recog_operand[0].
-        V is always set to 0.  C may or may not be set to 0 but that's ok
+      /* Insn sets the Z,N,V flags of CC to recog_operand[0].
+        C may or may not be set to 0 but that's ok
         because alter_cond will change tests to use EQ/NE.  */
       CC_STATUS_INIT;
-      cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY;
       cc_status.value1 = recog_operand[0];
       break;
 
@@ -1604,44 +1603,6 @@ notice_update_cc (body, insn)
     }
 }
 
-/* Return 1 if a previous compare needs to be re-issued.  This will happen
-   if the compare was deleted because the previous insn set it, but the
-   branch needs CC flags not set.
-
-   OP is the comparison being performed.  */
-
-int
-restore_compare_p (op)
-     rtx op;
-{
-  switch (GET_CODE (op))
-    {
-    case EQ:
-    case NE:
-      break;
-    case LT:
-    case LE:
-    case GT:
-    case GE:
-      if (cc_status.flags & CC_OVERFLOW_UNUSABLE)
-       return 1;
-      break;
-    case LTU:
-    case LEU:
-    case GTU:
-    case GEU:
-      /* If the carry flag isn't usable, the test should have been changed
-        by alter_cond.  */
-      if (cc_status.flags & CC_NO_CARRY)
-       abort ();
-      break;
-    default:
-      abort ();
-    }
-
-  return 0;
-}
-
 /* Recognize valid operators for bit instructions */
 
 int
@@ -2329,7 +2290,7 @@ get_shift_alg (cpu, shift_type, mode, count, assembler_p,
              *cc_valid_p = 0;
              return SHIFT_SPECIAL;
            }
-         else
+         else if (shift_type != SHIFT_ASHIFTRT)
            {
              *assembler_p = rotate_one[cpu][shift_type][shift_mode];
              if (TARGET_H8300S)

diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index acf0964..0ca5278 100644 (file)
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -229,18 +229,18 @@ do {                              \
    All registers that the compiler knows about must be given numbers,
    even those that are not normally considered general registers.  
 
-   Reg 8 does not correspond to any hardware register, but instead
+   Reg 9 does not correspond to any hardware register, but instead
    appears in the RTL as an argument pointer prior to reload, and is
    eliminated during reloading in favor of either the stack or frame
    pointer.  */
 
-#define FIRST_PSEUDO_REGISTER 9
+#define FIRST_PSEUDO_REGISTER 10
 
 /* 1 for registers that have pervasive standard uses
    and are not available for the register allocator.  */
 
 #define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 1, 1}
+  { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -253,19 +253,28 @@ do {                              \
    h8 destroys r0,r1,r2,r3.  */
 
 #define CALL_USED_REGISTERS \
-  { 1, 1, 1, 1, 0, 0, 0, 1, 1 }
+  { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1 }
 
 #define REG_ALLOC_ORDER \
-  { 2, 3, 0, 1, 4, 5, 6, 7, 8}
+  { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9}
+
+#define CONDITIONAL_REGISTER_USAGE     \
+{                                      \
+  if (!TARGET_H8300S)                  \
+    fixed_regs[8] = call_used_regs[8] = 1;\
+}
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
    to hold something of mode MODE.
 
    This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.  */
+   but can be less for certain modes in special long registers. 
+
+   We pretend the MAC register is 32bits -- we don't have any data
+   types on the H8 series to handle more than 32bits.  */
 
 #define HARD_REGNO_NREGS(REGNO, MODE)   \
-  ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 
 /* Value is 1 if hard register REGNO can hold a value of machine-mode
    MODE.
@@ -276,7 +285,7 @@ do {                                \
 
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
  (TARGET_H8300 ? (((REGNO)&1)==0) || (MODE==HImode) || (MODE==QImode) \
-  : 1)
+   : REGNO == 8 ? MODE == SImode : 1)
 
 /* Value is 1 if it is a good idea to tie two pseudo registers
    when one has mode MODE1 and one has mode MODE2.
@@ -304,7 +313,7 @@ do {                                \
 #define FRAME_POINTER_REQUIRED 0
 
 /* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 8
+#define ARG_POINTER_REGNUM 9
 
 /* Register in which static-chain is passed to a function.  */
 #define STATIC_CHAIN_REGNUM 3
@@ -330,7 +339,7 @@ do {                                \
    class that represents their union.  */
    
 enum reg_class {
-  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+  NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
@@ -338,7 +347,7 @@ enum reg_class {
 /* Give names of register classes as strings for dump file.   */
 
 #define REG_CLASS_NAMES \
-{ "NO_REGS", "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
+{ "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
 
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
@@ -347,26 +356,27 @@ enum reg_class {
 #define REG_CLASS_CONTENTS                     \
 {      0,              /* No regs      */      \
    0x0ff,              /* GENERAL_REGS */      \
-   0x1ff,              /* ALL_REGS     */      \
+   0x100,              /* MAC_REGS */          \
+   0x3ff,              /* ALL_REGS     */      \
 }
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
-   or could index an array.
-
-   ??? What about the ARG_POINTER_REGISTER? */
+   or could index an array.  */
 
-#define REGNO_REG_CLASS(REGNO)  GENERAL_REGS
+#define REGNO_REG_CLASS(REGNO) (REGNO != 8 ? GENERAL_REGS : MAC_REGS)
 
 /* The class value for index registers, and the one for base regs.  */
 
 #define INDEX_REG_CLASS NO_REGS
 #define BASE_REG_CLASS  GENERAL_REGS
 
-/* Get reg_class from a letter such as appears in the machine description.  */
+/* Get reg_class from a letter such as appears in the machine description. 
+
+   'a' is the MAC register.  */
 
-#define REG_CLASS_FROM_LETTER(C) (NO_REGS)
+#define REG_CLASS_FROM_LETTER(C) ((C) == 'a' ? MAC_REGS : NO_REGS)
 
 /* The letters I, J, K, L, M, N, O, P in a register constraint string
    can be used to stand for particular ranges of immediate operands.
@@ -422,7 +432,8 @@ enum reg_class {
    so define REGISTER_MOVE_COST to be > 2 so that reload never
    shortcuts.  */
 
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) 3
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)  \
+  (CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3)
 \f
 /* Stack layout; function entry, exit and calling.  */
 
@@ -731,7 +742,7 @@ struct rtx_def *function_arg();
 #define REGNO_OK_FOR_INDEX_P(regno) 0
 
 #define REGNO_OK_FOR_BASE_P(regno) \
-  ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
+  (((regno) < FIRST_PSEUDO_REGISTER && regno != 8) || reg_renumber[regno] >= 0)
 \f
 /* Maximum number of registers that can appear in a valid memory address.  */
 
@@ -1140,7 +1151,7 @@ readonly_data()                                           \
    This sequence is indexed by compiler's hard-register-number (see above).  */
 
 #define REGISTER_NAMES \
-{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "ap"}
+{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap"}
 
 #define ADDITIONAL_REGISTER_NAMES { { "r7", 7 } }
 

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index a1709ef..a583828 100644 (file)
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -86,7 +86,7 @@
 ;; none_0hit - insn does not affect cc but it does modify operand 0
 ;;     This attribute is used to keep track of when operand 0 changes.
 ;;     See the description of NOTICE_UPDATE_CC for more info.
-;; set - insn sets flags z,n.  v,c are set to 0.
+;; set - insn sets flags z,n,v.  c are set to 0.
 ;;     (c may not really be set to 0 but that's ok, we don't need it anyway).
 ;; set_zn_c0 - insn sets z,n to usable values.  v is unknown.  c may or may not
 ;;     be known (if it isn't that's ok, we don't need it anyway).
@@ -113,7 +113,7 @@
     return \"push.l    %S1\";
 }"
   [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
@@ -131,7 +131,7 @@
      [(const_int 2) (const_int 2) (const_int 2) (const_int 2)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand_dst" "")
@@ -159,7 +159,7 @@
   [(set_attr_alternative "length"
      [(const_int 2) (const_int 2) (const_int 2)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn_c0,set,set,set")])
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
    
 ;; movhi
 
@@ -177,7 +177,7 @@
     return \"push.l    %S1\";
 }"
   [(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
@@ -195,7 +195,7 @@
      [(const_int 2) (const_int 2) (const_int 2) (const_int 4)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand_dst" "")
@@ -223,7 +223,7 @@
   [(set_attr_alternative "length"
      [(const_int 2) (const_int 2) (const_int 4)
       (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
-   (set_attr "cc" "set_zn_c0,set,set,set")])
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
 
 ;; movsi
 
@@ -395,16 +395,22 @@
   [(set_attr "length" "4,4,8,8,4,4")
    (set_attr "cc" "clobber")])
 
-(define_insn "movsi_h8300h"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r")
-       (match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>"))]
-  "(TARGET_H8300H || TARGET_H8300S)
+(define_insn "movsi_h8300hs"
+  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,m,<,r,*a,*a,r")
+       (match_operand:SI 1 "general_operand_src" "I,r,im,r,r,>,I,r,*a"))]
+  "(TARGET_H8300S || TARGET_H8300H)
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
   "*
 {
   if (which_alternative == 0)
     return \"sub.l     %S0,%S0\";
+  if (which_alternative == 6)
+    return \"clrmac\";
+  if (which_alternative == 7)
+    return \"clrmac\;ldmac %1,macl\";
+  if (which_alternative == 8)
+    return \"stmac macl,%0\";
   if (GET_CODE (operands[1]) == CONST_INT)
     {
       int val = INTVAL (operands[1]);
@@ -433,8 +439,8 @@
     }
    return \"mov.l      %S1,%S0\";
 }"
-  [(set_attr "length" "2,2,10,10,4,4")
-   (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
+  [(set_attr "length" "2,2,10,10,4,4,2,6,4")
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,none_0hit,none_0hit,set_zn_c0")])
 
 (define_insn "movsf_h8300h"
   [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
@@ -450,7 +456,7 @@
    mov.l       %S1,%S0
    mov.l       %S1,%S0"
   [(set_attr "length" "2,2,10,10,4,4")
-   (set_attr "cc" "set_zn_c0,set,set,set,set,set")])
+   (set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
 \f
 ;; ----------------------------------------------------------------------
 ;; TEST INSTRUCTIONS
@@ -515,21 +521,21 @@
   ""
   "mov.b       %X0,%X0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn "tsthi"
   [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
   ""
   "mov.w       %T0,%T0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn "tstsi"
   [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
   "TARGET_H8300H || TARGET_H8300S"
   "mov.l       %S0,%S0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn "cmpqi"
   [(set (cc0)
@@ -591,7 +597,7 @@
   ""
   "add.b       %X2,%X0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set_zn_c0")])
+   (set_attr "cc" "set")])
 
 (define_expand "addhi3"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -625,7 +631,7 @@
    add.w       %T2,%T0
    mov.w        %T1,%T0\;add.w  %T2,%T0"
   [(set_attr "length" "4,2,6")
-   (set_attr "cc" "clobber,set_zn_c0,set_zn_c0")])
+   (set_attr "cc" "clobber,set,set")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -636,7 +642,7 @@
    add.w       %T2,%T0
    add.w       %T2,%T0"
   [(set_attr "length" "4,2")
-   (set_attr "cc" "set_zn_c0,set_zn_c0")])
+   (set_attr "cc" "set,set")])
 
 (define_expand "addsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -681,7 +687,7 @@
    add.l       %S2,%S0
    add.l       %S2,%S0"
   [(set_attr "length" "6,2")
-   (set_attr "cc" "set_zn_c0,set_zn_c0")])
+   (set_attr "cc" "set,set")])
 
 ;; ----------------------------------------------------------------------
 ;; SUBTRACT INSTRUCTIONS
@@ -696,7 +702,7 @@
    sub.b       %X2,%X0
    add.b       %G2,%X0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set_zn_c0")])
+   (set_attr "cc" "set")])
 
 (define_expand "subhi3"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -734,7 +740,7 @@
    sub.w       %T2,%T0
    add.b       %E2,%s0\;addx   %F2,%t0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn_c0,clobber")])
+   (set_attr "cc" "set,clobber")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r,&r")
@@ -745,7 +751,7 @@
    sub.w       %T2,%T0
    sub.w       %T2,%T0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn_c0,set_zn_c0")])
+   (set_attr "cc" "set,set")])
 
 (define_expand "subsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -792,7 +798,7 @@
    sub.l       %S2,%S0
    sub.l       %S2,%S0"
   [(set_attr "length" "2,6")
-   (set_attr "cc" "set_zn_c0,set_zn_c0")])
+   (set_attr "cc" "set,set")])
 \f
 ;; ----------------------------------------------------------------------
 ;; MULTIPLY INSTRUCTIONS
@@ -836,6 +842,38 @@
   [(set_attr "length" "2")
    (set_attr "cc" "none_0hit")])
 
+;; This is a "bridge" instruction.  Combine can't cram enough insns
+;; together to crate a MAC instruction directly, but it can create
+;; this instruction, which then allows combine to create the real
+;; MAC insn.
+;;
+;; Unfortunately, if combine doesn't create a MAC instruction, this
+;; insn must generate reasonably correct code.  Egad.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=a")
+       (mult:SI
+         (sign_extend:SI
+           (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
+         (sign_extend:SI
+           (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
+  "TARGET_H8300S"
+  "clrmac\;mac %2,%1"
+  [(set_attr "length" "6")
+   (set_attr "cc" "none_0hit")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=a")
+       (plus (mult:SI
+         (sign_extend:SI (mem:HI
+           (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
+         (sign_extend:SI (mem:HI
+           (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
+             (match_operand:SI 3 "register_operand" "0")))]
+  "TARGET_H8300S"
+  "mac %2,%1"
+  [(set_attr "length" "4")
+   (set_attr "cc" "none_0hit")])
+
 ;; ----------------------------------------------------------------------
 ;; DIVIDE INSTRUCTIONS
 ;; ----------------------------------------------------------------------
@@ -947,7 +985,7 @@
    and %X2,%X0
    bclr        %W2,%R0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,none_0hit")])
+   (set_attr "cc" "set_zn_c0,none_0hit")])
 
 (define_expand "andqi3"
   [(set (match_operand:QI 0 "bit_operand" "")
@@ -1051,7 +1089,7 @@
    or  %X2,%X0
    bset        %V2,%R0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,none_0hit")])
+   (set_attr "cc" "set_zn_c0,none_0hit")])
 
 (define_expand "iorqi3"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
@@ -1137,7 +1175,7 @@
    xor %X2,%X0
    bnot        %V2,%R0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,none_0hit")])
+   (set_attr "cc" "set_zn_c0,none_0hit")])
 
 (define_expand "xorqi3"
   [(set (match_operand:QI 0 "bit_operand" "=r,U")
@@ -1292,7 +1330,7 @@
   ""
   "not %X0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_insn "one_cmplhi2"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1436,11 +1474,6 @@
   ""
   "*
 {
-  /* If we erroneously deleted a compare insn (which can happen if we need
-     CC bits set that aren't), emit the compare.  */
-  if (restore_compare_p (operands[1]))
-    return 0;
-
   if (get_attr_length (insn) == 2) 
     return \"b%j1      %l0\";
   else if (get_attr_length (insn) == 4) 
@@ -1460,11 +1493,6 @@
   ""
   "*
 {
-  /* If we erroneously deleted a compare insn (which can happen if we need
-     CC bits set that aren't), emit the compare.  */
-  if (restore_compare_p (operands[1]))
-    return 0;
-
   if (get_attr_length (insn) == 2) 
     return \"b%k1      %l0\";
   else if (get_attr_length (insn) == 4) 
@@ -1661,7 +1689,7 @@
   extu.l       %S0
   mov.w        %T1,%T0\;extu.l %S0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,set")])
+   (set_attr "cc" "set_zn_c0,set_zn_c0")])
 
 (define_expand "extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -1687,7 +1715,7 @@
   exts.w       %T0
   mov.b        %R1,%s0\;exts.w %T0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,set")])
+   (set_attr "cc" "set_zn_c0,set_zn_c0")])
 
 ;; The compiler can synthesize a 300H variant of this which is
 ;; just as efficient as one that we'd create
@@ -1744,7 +1772,7 @@
   exts.l       %S0
   mov.w        %T1,%T0\;exts.l %S0"
   [(set_attr "length" "2,4")
-   (set_attr "cc" "set,set")])
+   (set_attr "cc" "set_zn_c0,set_zn_c0")])
 \f
 ;; ----------------------------------------------------------------------
 ;; SHIFTS
@@ -2214,7 +2242,7 @@
   "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
   "mov.w       @(%u4,%T1),%T0"
   [(set_attr "length" "6")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_peephole
   [(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
@@ -2226,7 +2254,7 @@
   "(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
   "mov.w       %T0,@(%u4,%T1)"
   [(set_attr "length" "6")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 ;; Notice a move which could be post incremented.
 
@@ -2237,7 +2265,7 @@
   "REGNO(operands[1]) != REGNO(operands[0])"
   "mov.b       @%T1+,%X0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_peephole 
   [(set (match_operand:HI 0 "register_operand" "")
@@ -2246,7 +2274,7 @@
   "REGNO(operands[1]) != REGNO(operands[0])"
   "mov.w       @%T1+,%T0"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 ;; Notice a move which could be predecremented.
 
@@ -2258,7 +2286,7 @@
   "REGNO(operands[1]) != REGNO(operands[0])"
   "mov.b       %X0,@-%T1"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])
 
 (define_peephole 
   [(set (match_operand:HI 1 "register_operand" "")
@@ -2268,5 +2296,5 @@
   "REGNO(operands[1]) != REGNO(operands[0])"
   "mov.w       %T0,@-%T1"
   [(set_attr "length" "2")
-   (set_attr "cc" "set")])
+   (set_attr "cc" "set_zn_c0")])