* config/s390/s390.md ("doloop_si64"): Reload input value directly

	into the register being decremented.
	("doloop_si31", "doloop_di"): Likewise.
	("*doloop_si_long"): Adapt pattern.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@94078 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 87c472f..5d3e553 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2005-01-21  Ulrich Weigand  <uweigand@de.ibm.com>
 
+       * config/s390/s390.md ("doloop_si64"): Reload input value directly
+       into the register being decremented.
+       ("doloop_si31", "doloop_di"): Likewise.
+       ("*doloop_si_long"): Adapt pattern.
+
+2005-01-21  Ulrich Weigand  <uweigand@de.ibm.com>
+
        * config/s390/s390.h (HARD_REGNO_NREGS): Fix computation for
        access registers.
        (CLASS_MAX_NREGS): Likewise.

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index bc827bd..4b8b58a 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -7266,7 +7266,7 @@
           (pc)))
    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
         (plus:SI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:SI 3 "=X,&d"))
+   (clobber (match_scratch:SI 3 "=X,&1"))
    (clobber (reg:CC 33))]
   "TARGET_CPU_ZARCH"
 {
@@ -7280,8 +7280,7 @@
   "&& reload_completed
    && (! REG_P (operands[2])
        || ! rtx_equal_p (operands[1], operands[2]))"
-  [(set (match_dup 3) (match_dup 1))
-   (parallel [(set (reg:CCAN 33)
+  [(parallel [(set (reg:CCAN 33)
                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
                                  (const_int 0)))
               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
@@ -7305,7 +7304,7 @@
           (pc)))
    (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
         (plus:SI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:SI 3 "=X,&d"))
+   (clobber (match_scratch:SI 3 "=X,&1"))
    (clobber (reg:CC 33))]
   "!TARGET_CPU_ZARCH"
 {
@@ -7319,8 +7318,7 @@
   "&& reload_completed
    && (! REG_P (operands[2])
        || ! rtx_equal_p (operands[1], operands[2]))"
-  [(set (match_dup 3) (match_dup 1))
-   (parallel [(set (reg:CCAN 33)
+  [(parallel [(set (reg:CCAN 33)
                    (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
                                  (const_int 0)))
               (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
@@ -7347,7 +7345,7 @@
           (pc)))
    (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
         (plus:SI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:SI 3 "=X,&d"))
+   (clobber (match_scratch:SI 3 "=X,&1"))
    (clobber (reg:CC 33))]
   "!TARGET_CPU_ZARCH"
 {
@@ -7369,9 +7367,9 @@
               (const_int 1))
           (label_ref (match_operand 0 "" ""))
           (pc)))
-   (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r")
+   (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
         (plus:DI (match_dup 1) (const_int -1)))
-   (clobber (match_scratch:DI 3 "=X,&d"))
+   (clobber (match_scratch:DI 3 "=X,&1"))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
 {
@@ -7385,8 +7383,7 @@
   "&& reload_completed
    && (! REG_P (operands[2])
        || ! rtx_equal_p (operands[1], operands[2]))"
-  [(set (match_dup 3) (match_dup 1))
-   (parallel [(set (reg:CCAN 33)
+  [(parallel [(set (reg:CCAN 33)
                    (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
                                  (const_int 0)))
               (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])