PR target/17245

	* config/sparc/sparc.c (input_operand): Remove redundant code
	for handling LO_SUM.
	(legitimate_address_p) <REG+REG>: Do not recheck TARGET_V9.
	<LO_SUM>: If LO_SUM is offsettable, accept it for TFmode on V9.
	Otherwise only accept it for TFmode if quad move insns are available.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@88753 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5bb44a5..161ead2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2004-10-08  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+       PR target/17245
+       * config/sparc/sparc.c (input_operand): Remove redundant code
+       for handling LO_SUM.
+       (legitimate_address_p) <REG+REG>: Do not recheck TARGET_V9.
+       <LO_SUM>: If LO_SUM is offsettable, accept it for TFmode on V9.
+       Otherwise only accept it for TFmode if quad move insns are available.
+
 2004-10-08  Kazu Hirata  <kazu@cs.umass.edu>
 
        * tree-cfg.c (tree_forwarder_block_p): Reorder checks so that

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 69a2aaf..3f75954 100644 (file)
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1547,23 +1547,7 @@ input_operand (rtx op, enum machine_mode mode)
 
   /* Check for valid MEM forms.  */
   if (GET_CODE (op) == MEM)
-    {
-      rtx inside = XEXP (op, 0);
-
-      if (GET_CODE (inside) == LO_SUM)
-       {
-         /* We can't allow these because all of the splits
-            (eventually as they trickle down into DFmode
-            splits) require offsettable memory references.  */
-         if (! TARGET_V9
-             && GET_MODE (op) == TFmode)
-           return 0;
-
-         return (register_operand (XEXP (inside, 0), Pmode)
-                 && CONSTANT_P (XEXP (inside, 1)));
-       }
-      return memory_address_p (mode, inside);
-    }
+    return memory_address_p (mode, XEXP (op, 0));
 
   return 0;
 }
@@ -3516,15 +3500,14 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
       else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
               && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
        {
-         /* We prohibit REG + REG for TFmode when there are no instructions
-            which accept REG+REG instructions.  We do this because REG+REG
-            is not an offsetable address.  If we get the situation in reload
+         /* We prohibit REG + REG for TFmode when there are no quad move insns
+            and we consequently need to split.  We do this because REG+REG
+            is not an offsettable address.  If we get the situation in reload
             where source and destination of a movtf pattern are both MEMs with
             REG+REG address, then only one of them gets converted to an
-            offsetable address.  */
+            offsettable address.  */
          if (mode == TFmode
-             && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
-                  && TARGET_HARD_QUAD))
+             && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
            return 0;
 
          /* We prohibit REG + REG on ARCH32 if not optimizing for
@@ -3557,10 +3540,25 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
       if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
        return 0;
 
-      /* We can't allow TFmode, because an offset greater than or equal to the
-         alignment (8) may cause the LO_SUM to overflow if !v9.  */
-      if (mode == TFmode && !TARGET_V9)
-       return 0;
+      if (USE_AS_OFFSETABLE_LO10)
+       {
+         /* We can't allow TFmode, because an offset greater than or equal to
+            the alignment (8) may cause the LO_SUM to overflow if !v9.  */
+         if (mode == TFmode && ! TARGET_V9)
+           return 0;
+       }
+      else
+        {
+         /* We prohibit LO_SUM for TFmode when there are no quad move insns
+            and we consequently need to split.  We do this because LO_SUM
+            is not an offsettable address.  If we get the situation in reload
+            where source and destination of a movtf pattern are both MEMs with
+            LO_SUM address, then only one of them gets converted to an
+            offsettable address.  */
+         if (mode == TFmode
+             && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
+           return 0;
+       }
     }
   else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
     return 1;

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 144d160..81dbc32 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2004-10-08  Christian Ehrhardt  <ehrhardt@mathematik.uni-ulm.de>
+
+       * gcc.dg/ultrasp11.c: New test.
+
 2004-10-08  Michael Matz  <matz@suse.de>
 
        * gcc.dg/doloop-2.c: New test.

diff --git a/gcc/testsuite/gcc.dg/ultrasp11.c b/gcc/testsuite/gcc.dg/ultrasp11.c
new file mode 100644 (file)
index 0000000..8f279f7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/ultrasp11.c
@@ -0,0 +1,25 @@
+/* PR target/17245 */
+/* Origin: <aaronw@net.com> */
+/* Testcase by Christian Ehrhardt <ehrhardt@mathematik.uni-ulm.de> */
+/* { dg-do compile { target sparc*-*-* } } */
+/* { dg-options "-O -mcpu=v9" } */
+
+/* This used to fail on 32-bit Ultrasparc because reload was emitting
+   a move insn that doesn't satisfy its constraints.  */
+
+int n; 
+double range ;
+double bin ;
+double wmean;
+
+double f ()
+{
+  int i ;
+  long double W = 0 ;
+  for ( i = 0 ; i < n ; i ++) {
+    double xi = range;
+    double wi = bin;
+    W += wi ;
+    wmean += ( xi - wmean) * ( wi / W);
+  }
+}