+2001-11-01 Kazu Hirata <kazu@hxi.com>
+
+ * config/m68hc11/m68hc11.c: Fix comment formatting.
+ * config/m68hc11/m68hc11.h: Likewise.
+ * config/m68hc11/m68hc11.md: Likewise.
+
2001-11-01 Neil Booth <neil@daikokuya.demon.co.uk>
* c-typeck.c (default_conversion): Retain the original expression
rtx m68hc11_soft_tmp_reg;
-/* Must be set to 1 to produce debug messages. */
+/* Must be set to 1 to produce debug messages. */
int debug_m6811 = 0;
extern FILE *asm_out_file;
}
\f
-/* Reload and register operations. */
+/* Reload and register operations. */
static const char *const reg_class_names[] = REG_CLASS_NAMES;
mode = GET_MODE (operands[1]);
- /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
+ /* Input reload of indirect addressing (MEM (PLUS (REG) (CONST))). */
if (A_REG_P (operands[0]) && memory_reload_operand (operands[1], mode))
{
rtx big_offset = XEXP (XEXP (operands[1], 0), 1);
}
}
- /* Use the normal gen_movhi pattern. */
+ /* Use the normal gen_movhi pattern. */
return 0;
}
int named ATTRIBUTE_UNUSED;
{
return ((type && TREE_CODE (type) == ARRAY_TYPE)
- /* Consider complex values as aggregates, so care for TCmode. */
+ /* Consider complex values as aggregates, so care for TCmode. */
/*|| GET_MODE_SIZE (mode) > 4 SCz, temporary */
/*|| (type && AGGREGATE_TYPE_P (type))) */ );
}
}
/* Scan forward to see if the register is set in some insns and never
- used since then. */
+ used since then. */
for (p = x /*NEXT_INSN (x) */ ; p; p = NEXT_INSN (p))
{
rtx body;
return 1;
}
- /* Register is used (may be in source or in dest). */
+ /* Register is used (may be in source or in dest). */
if (reg_mentioned_p (reg, p)
|| (x_reg != 0 && GET_MODE (p) == SImode
&& reg_mentioned_p (x_reg, p)))
't' generate the temporary scratch register. The operand is
ignored.
'T' generate the low-part temporary scratch register. The operand is
- ignored. */
+ ignored. */
void
print_operand (file, op, letter)
}
}
- /* The logical operation is similar to a copy. */
+ /* The logical operation is similar to a copy. */
else if (need_copy)
{
rtx src;
}
/* Some moves to a hard register are special. Not all of them
are really supported and we have to use a temporary
- location to provide them (either the stack of a temp var). */
+ location to provide them (either the stack of a temp var). */
if (H_REG_P (operands[0]))
{
switch (REGNO (operands[0]))
}
else
{
- /* %t means *ZTMP scratch register. */
+ /* %t means *ZTMP scratch register. */
output_asm_insn ("sty\t%t1", operands);
output_asm_insn ("ldd\t%t1", operands);
}
{
/* Move a register or memory to the same location.
This is possible because such insn can appear
- in a non-optimizing mode. */
+ in a non-optimizing mode. */
if (operands[0] == operands[1] || rtx_equal_p (operands[0], operands[1]))
{
cc_status = cc_prev_status;
\f
-/* Machine Specific Reorg. */
+/* Machine Specific Reorg. */
/* Z register replacement:
/* Analyze the insn to find out which replacement register to use and
the boundaries of the replacement.
Returns 0 if we reached the last insn to be replaced, 1 if we can
- continue replacement in next insns. */
+ continue replacement in next insns. */
static int
m68hc11_check_z_replacement (insn, info)
fatal_insn ("Cannot do z-register replacement", insn);
}
- /* Likewise for (REG:QI Z). */
+ /* Likewise for (REG:QI Z). */
if (reg_mentioned_p (z_reg, insn))
{
if (replace_reg_qi == NULL_RTX)
/* Cost functions. */
-/* Cost of moving memory. */
+/* Cost of moving memory. */
int
m68hc11_memory_move_cost (mode, class, in)
enum machine_mode mode;
switch (GET_CODE (addr))
{
case REG:
- /* Make the cost of hard registers and specially SP, FP small. */
+ /* Make the cost of hard registers and specially SP, FP small. */
if (REGNO (addr) < FIRST_PSEUDO_REGISTER)
cost = 0;
else
\f
/* print_options - called at the start of the code generation for a
- module. */
+ module. */
extern char *asm_file_name;
#define inhibit_libc
/* Forward type declaration for prototypes definitions.
- rtx_ptr is equivalent to rtx. Can't use the same name. */
+ rtx_ptr is equivalent to rtx. Can't use the same name. */
struct rtx_def;
typedef struct rtx_def *rtx_ptr;
/* We can't declare enum machine_mode forward nor include 'machmode.h' here.
Prototypes defined here will use an int instead. It's better than no
- prototype at all. */
+ prototype at all. */
typedef int enum_machine_mode;
/*****************************************************************************
#define BYTES_BIG_ENDIAN 1
/* Define this if most significant bit is lowest numbered
- in instructions that operate on numbered bit-fields. */
+ in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0
/* Define this if most significant word of a multiword number is numbered. */
#define FUNCTION_BOUNDARY 8
/* Biggest alignment that any data type can require on this machine,
- in bits. */
+ in bits. */
#define BIGGEST_ALIGNMENT 8
/* Alignment of field after `int : 0' in a structure. */
appropriate sizes. */
#define MAX_FIXED_MODE_SIZE 64
-/* Floats are checked in a generic way. */
+/* Floats are checked in a generic way. */
/* #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) */
(see Z register replacement notes in m68hc11.c). */
#define SOFT_Z_REGNUM 11
-/* The soft-register which is used to save either X or Y. */
+/* The soft-register which is used to save either X or Y. */
#define SOFT_SAVED_XY_REGNUM 12
/* A fake clobber register for 68HC12 patterns. */
"*_.d25", "*_.d26", "*_.d27", "*_.d28", \
"*_.d29", "*_.d30", "*_.d31", "*_.d32"
-/* First available soft-register for GCC. */
+/* First available soft-register for GCC. */
#define SOFT_REG_FIRST (SOFT_SAVED_XY_REGNUM+2)
-/* Last available soft-register for GCC. */
+/* Last available soft-register for GCC. */
#define SOFT_REG_LAST (SOFT_REG_FIRST+MAX_SOFT_REG_COUNT)
#define SOFT_FP_REGNUM (SOFT_REG_LAST)
#define SOFT_AP_REGNUM (SOFT_FP_REGNUM+1)
/* Number of actual hardware registers. The hardware registers are assigned
numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers, even
- those that are not normally considered general registers. */
+ those that are not normally considered general registers. */
#define FIRST_PSEUDO_REGISTER (SOFT_REG_LAST+2)
/* 1 for registers that have pervasive standard uses and are not available
- for the register allocator. */
+ for the register allocator. */
#define FIXED_REGISTERS \
{0, 0, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1,1, 1, SOFT_REG_FIXED, 1, 1}
/* X, D, Y, SP,PC,A, B, CCR, Z, FP,ZTMP,ZR,XYR, FK, D1 - D32, SOFT-FP, AP */
/* Define this macro to change register usage conditional on target flags.
The soft-registers are disabled or enabled according to the
- -msoft-reg-count=<n> option. */
+ -msoft-reg-count=<n> option. */
#define CONDITIONAL_REGISTER_USAGE (m68hc11_conditional_register_usage ())
X_REGS, /* 16-bit X register */
Y_REGS, /* 16-bit Y register */
SP_REGS, /* 16 bit stack pointer */
- DA_REGS, /* 8-bit A reg. */
- DB_REGS, /* 8-bit B reg. */
+ DA_REGS, /* 8-bit A reg. */
+ DB_REGS, /* 8-bit B reg. */
Z_REGS, /* 16-bit fake Z register */
- D8_REGS, /* 8-bit A or B reg. */
+ D8_REGS, /* 8-bit A or B reg. */
Q_REGS, /* 8-bit (byte (QI)) data (A, B or D) */
D_OR_X_REGS, /* D or X register */
D_OR_Y_REGS, /* D or Y register */
LIM_REG_CLASSES
};
-/* alias GENERAL_REGS to G_REGS. */
+/* alias GENERAL_REGS to G_REGS. */
#define GENERAL_REGS G_REGS
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
+/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"D_REGS", \
This space can either be allocated by the caller or be a part of the
machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE'
- says which. */
+ says which. */
/* #define REG_PARM_STACK_SPACE(FNDECL) 2 */
/* Define this macro if REG_PARM_STACK_SPACE is defined but stack
We have two registers that are eliminated on the 6811. The psuedo arg
pointer and pseudo frame pointer registers can always be eliminated;
- they are replaced with either the stack or the real frame pointer. */
+ they are replaced with either the stack or the real frame pointer. */
#define ELIMINABLE_REGS \
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may be
accessed via the stack pointer) in functions that seem suitable.
- This is computed in `reload', in reload1.c. */
+ This is computed in `reload', in reload1.c. */
#define FRAME_POINTER_REQUIRED 0
/* Given FROM and TO register numbers, say whether this elimination is allowed.
/* If we generate an insn to push BYTES bytes, this says how many the
stack pointer really advances by. No rounding or alignment needed
- for MC6811. */
+ for MC6811. */
#define PUSH_ROUNDING(BYTES) (BYTES)
/* Value is 1 if returning from a function call automatically pops the
an identifier node for the subroutine name.
The standard MC6811 call, with arg count word, includes popping the
- args as part of the call template. */
+ args as part of the call template. */
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
/* Nonzero if type TYPE should be returned in memory.
The pointer is passed in whatever way is appropriate for passing a pointer
to that type.
- 64-bit numbers are passed by reference. */
+ 64-bit numbers are passed by reference. */
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
m68hc11_function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED))
does not make a copy. Instead, it passes a pointer to the "live"
value. The called function must not modify this value. If it can
be determined that the value won't be modified, it need not make a
- copy; otherwise a copy must be made. */
+ copy; otherwise a copy must be made. */
#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
((NAMED) && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a
- function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
+ function whose data type is FNTYPE. For a library call, FNTYPE is 0. */
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
(m68hc11_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
asm_fprintf (FILE, "\tldy LP%d\n\tjsr mcount\n", (LABELNO))
/* Output assembler code to FILE to initialize this source file's
- basic block profiling info, if that has not already been done. */
+ basic block profiling info, if that has not already been done. */
#define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
m68hc11_function_block_profiler(FILE, BLOCK_OR_LABEL)
indexed N,X
--------------------------------------------------------------*/
-/* The range of index that is allowed by indirect addressing. */
+/* The range of index that is allowed by indirect addressing. */
#define VALID_MIN_OFFSET m68hc11_min_offset
#define VALID_MAX_OFFSET m68hc11_max_offset
(((GET_CODE (X) == PRE_DEC) || (GET_CODE (X) == POST_INC)) \
&& SP_REG_P (XEXP (X, 0)))
-/* Go to ADDR if X is a valid address. */
+/* Go to ADDR if X is a valid address. */
#ifndef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
#define PRINT_OPERAND(FILE, X, CODE) \
print_operand (FILE, X, CODE)
-/* Print a memory operand whose address is X, on file FILE. */
+/* Print a memory operand whose address is X, on file FILE. */
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
print_operand_address (FILE, ADDR)
#undef ASM_OUTPUT_REG_PUSH
#undef ASM_OUTPUT_REG_POP
-/* This is how to output an element of a case-vector that is relative. */
+/* This is how to output an element of a case-vector that is relative. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
asm_fprintf (FILE, "\t%s\tL%d-L%d\n", ASM_SHORT, VALUE, REL)
-/* This is how to output an element of a case-vector that is absolute. */
+/* This is how to output an element of a case-vector that is absolute. */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
asm_fprintf (FILE, "\t%s\t.L%d\n", ASM_SHORT, VALUE)
/* Assembler Commands for Exception Regions. */
/* Default values provided by GCC should be ok. Assumming that DWARF-2
- frame unwind info is ok for this platform. */
+ frame unwind info is ok for this platform. */
-/* How to renumber registers for dbx and gdb. */
+/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(REGNO) \
((REGNO))
an empty string, or any arbitrary string (such as ".", ".L%", etc)
without having to make any other changes to account for the specific
definition. Note it is a string literal, not interpreted by printf
- and friends. */
+ and friends. */
#define LOCAL_LABEL_PREFIX "."
/* The prefix for immediate operands. */
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE Pmode
-/* Specify the tree operation to be used to convert reals to integers. */
+/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* This flag, if defined, says the same insns that convert to a signed fixnum
rtx push = m68hc11_gen_lowpart (HImode, low);
rtx src = operands[1];
- /* Source operand must be in a hard register. */
+ /* Source operand must be in a hard register. */
if (!H_REG_P (src))
{
src = gen_rtx (REG, QImode, REGNO (operands[2]));
}
/* Source is in D, we can push B then one word of 0 and we do
- a correction on the stack pointer. */
+ a correction on the stack pointer. */
if (D_REG_P (src))
{
emit_move_insn (m68hc11_gen_lowpart (QImode, push), src);
rtx low2 = m68hc11_gen_lowpart (HImode, low);
rtx src = operands[1];
- /* Source operand must be in a hard register. */
+ /* Source operand must be in a hard register. */
if (!H_REG_P (src))
{
src = gen_rtx (REG, QImode, REGNO (operands[2]));
else if (X_REG_P (operands[0]))
{
/* X can be used as an indexed addressing in the source.
- Get the value before clearing it. */
+ Get the value before clearing it. */
if (reg_mentioned_p (ix_reg, operands[1]))
{
output_asm_insn (\"ldab\\t%b1\", operands);
else
{
/* X can be used as a indexed addressing in the source.
- Get the value before clearing it. */
+ Get the value before clearing it. */
x_reg_used = reg_mentioned_p (ix_reg, operands[1]);
if (x_reg_used)
{
}
ops[2] = gen_label_rtx ();
- /* ldx preserves the carry, propagate it by incrementing X directly. */
+ /* ldx preserves the carry, propagate it by incrementing X directly. */
output_asm_insn (\"addd\\t%0\", ops);
if (!X_REG_P (operands[2]))
output_asm_insn (\"ldx\\t%1\", ops);
output_asm_insn (\"clra\", ops);
}
- /* ldx preserves the carry, propagate it by incrementing X directly. */
+ /* ldx preserves the carry, propagate it by incrementing X directly. */
output_asm_insn (\"addb\\t%b0\", ops);
output_asm_insn (\"adca\\t%h1\", ops);
if (!X_REG_P (operands[2]))
}
/* For X and Y increment, the flags are not complete. Only the Z flag
- is updated. For SP increment, flags are not changed. */
+ is updated. For SP increment, flags are not changed. */
if (SP_REG_P (operands[0]))
{
cc_status = cc_prev_status;
if (GET_CODE (operands[2]) != CONST_INT)
{
/* Adding to an address register or with another/same register
- is not possible. This must be replaced. */
+ is not possible. This must be replaced. */
if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
return \"#\";
output_asm_insn (\"xgdx\", operands);
/* The status flags correspond to the addd. xgdx/y and tx/ys do not
- modify the flags. */
+ modify the flags. */
output_asm_insn (\"txs\", operands);
return \"xgdx\";
}
/* Need to transfer to SP to X,Y and then to D register.
- Register X,Y is lost, this is specified by the (clobber) statement. */
+ Register X,Y is lost, this is specified by the (clobber) statement. */
output_asm_insn (\"ts%3\", operands);
output_asm_insn (\"xgd%3\", operands);
output_asm_insn (\"subd\\t%2\", operands);
output_asm_insn (\"xgd%3\", operands);
/* The status flags correspond to the addd. xgdx/y and tx/ys do not
- modify the flags. */
+ modify the flags. */
return \"t%3s\";
}")
"*
{
/* Adding to an address register or with another/same register
- is not possible. This must be replaced. */
+ is not possible. This must be replaced. */
if (A_REG_P (operands[0]) || H_REG_P (operands[2]))
return \"#\";
(match_operand:HI 2 "general_operand" "dAuim")]))]
"z_replacement_completed == 2
/* If we are adding a small constant to X or Y, it's
- better to use one or several inx/iny instructions. */
+ better to use one or several inx/iny instructions. */
&& !(GET_CODE (operands[3]) == PLUS
&& ((TARGET_M6812
&& (immediate_operand (operands[2], HImode)
(parallel [(set (reg:HI D_REGNUM) (match_dup 0))
(set (match_dup 0) (reg:HI D_REGNUM))])]
"
- /* Save the operand2 in a temporary location and use it. */
+ /* Save the operand2 in a temporary location and use it. */
if ((H_REG_P (operands[2])
|| reg_mentioned_p (operands[0], operands[2]))
&& !(SP_REG_P (operands[2]) && GET_CODE (operands[3]) == PLUS))
(match_operand:HI 2 "general_operand" "dAuim")]))]
"z_replacement_completed == 2
/* If we are adding a small constant to X or Y, it's
- better to use one or several inx/iny instructions. */
+ better to use one or several inx/iny instructions. */
&& !(GET_CODE (operands[3]) == PLUS
&& ((TARGET_M6812
&& (immediate_operand (operands[2], HImode)
&& !rtx_equal_p (operands[0], operands[1]))
|| reg_mentioned_p (operands[0], operands[1]))
{
- /* Move to the destination register, before the xgdx. */
+ /* Move to the destination register, before the xgdx. */
operands[4] = gen_rtx (REG, GET_MODE (operands[1]),
REGNO (operands[0]));
operands[5] = operands[1];
- /* Apply the operation on D. */
+ /* Apply the operation on D. */
operands[3] = gen_rtx (REG, GET_MODE (operands[1]), HARD_D_REGNUM);
}
else
{
- /* Generate a copy to same register (nop). */
+ /* Generate a copy to same register (nop). */
operands[4] = operands[5] = operands[0];
operands[3] = operands[1];
}
(match_operand:QI 2 "general_operand" "dxyuim")]))]
"z_replacement_completed == 2
/* Reject a (plus:QI (reg:QI X) (const_int 1|-1)) because the
- incqi pattern generates a better code. */
+ incqi pattern generates a better code. */
&& !(GET_CODE (operands[3]) == PLUS
&& GET_CODE (operands[2]) == CONST_INT
&& (INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == -1))"
register appears in the source, we have to save the operand[2]
value in a temporary location and then use that temp.
Otherwise, it's ok and we generate a (set (D) (D)) that
- will result in a nop. */
+ will result in a nop. */
if (H_REG_P (operands[2]))
{
operands[5] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);
&& !rtx_equal_p (operands[0], operands[1]))
|| reg_mentioned_p (operands[0], operands[1]))
{
- /* Move to the destination register, before the xgdx. */
+ /* Move to the destination register, before the xgdx. */
operands[4] = operands[0];
operands[5] = operands[1];
- /* Apply the operation on D. */
+ /* Apply the operation on D. */
operands[6] = gen_rtx (REG, QImode, HARD_D_REGNUM);
}
else
"
{
/* The result pattern only works for D register.
- Generate 2 one_cmplhi2 instructions. */
+ Generate 2 one_cmplhi2 instructions. */
if (!D_REG_P (operands[0]))
{
rtx ops[2];
output_asm_insn (\"clrb\", operands);
output_asm_insn (\"rola\", operands);
- /* Clear A without clearing the carry flag. */
+ /* Clear A without clearing the carry flag. */
output_asm_insn (\"tba\", operands);
output_asm_insn (\"bcc\\t%l0\", ops);
output_asm_insn (\"coma\", operands);
output_asm_insn (\"asrb\", operands);
val--;
}
- /* Status is ok. */
+ /* Status is ok. */
return \"\";
}
if (val == 7)
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