2006-09-20 Eric Christopher <echristo@apple.com>

        * config/i386/i386.c (x86_fisttp): Remove.
        * config/i386/i386.h (x86_fisttp): Ditto.
        (TARGET_FISTTP): Ditto.

2006-09-20  Eric Christopher  <echristo@apple.com>

        * gcc.target/i386/sse3-not-fisttp.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@117076 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a961b5c..f7361e3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2006-09-20  Eric Christopher  <echristo@apple.com>
+
+       * config/i386/i386.c (x86_fisttp): Remove.
+       * config/i386/i386.h (x86_fisttp): Ditto.
+       (TARGET_FISTTP): Ditto.
+
 2006-09-19  Eric Christopher  <echristo@apple.com>
 
        * doc/tm.texi (OBJC_JBLEN): Describe.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index daba68d..cdbd0c6 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -743,7 +743,6 @@ const int x86_double_with_add = ~m_386;
 const int x86_use_bit_test = m_386;
 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
-const int x86_fisttp = m_NOCONA;
 const int x86_3dnow_a = m_ATHLON_K8;
 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
 /* Branch hints were put in P4 based on simulation result. But

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 9474964..f2e6ce0 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -142,7 +142,7 @@ extern const struct processor_costs *ix86_cost;
 
 #define TUNEMASK (1 << ix86_tune)
 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
-extern const int x86_use_bit_test, x86_cmove, x86_fisttp, x86_deep_branch;
+extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
 extern const int x86_branch_hints, x86_unroll_strlen;
 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
@@ -175,8 +175,7 @@ extern int x86_prefetch_sse;
 /* For sane SSE instruction set generation we need fcomi instruction.  It is
    safe to enable all CMOVE instructions.  */
 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
-#define TARGET_FISTTP (((x86_fisttp & (1 << ix86_arch)) || TARGET_SSE3) \
-                       && TARGET_80387)
+#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2658cc3..5a7a540 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2006-09-20  Eric Christopher  <echristo@apple.com>
+
+       * gcc.target/i386/sse3-not-fisttp.c: New.
+
 2006-09-19  Jack Howarth  <howarth@bromo.med.uc.edu>
 
        * gfortran.dg/vect/vect-5.f90: Don't xfail lp64.

diff --git a/gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c b/gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c
new file mode 100644 (file)
index 0000000..2f3261a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c
@@ -0,0 +1,24 @@
+/* Test that we don't generate a fisttp instruction when -mno-sse3.  */
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O -march=nocona -mno-sse3" } */
+/* { dg-final { scan-assembler-not "fisttp" } } */
+struct foo
+{
+ long a;
+ long b;
+};
+
+extern double c;
+
+extern unsigned long long baz (void);
+
+int
+walrus (const struct foo *input)
+{
+    unsigned long long d;
+
+    d = baz ()
+      + (unsigned long long) (((double) input->a * 1000000000
+                             + (double) input->b) * c);
+    return (d ? 1 : 0);
+}