(zero_extendqi[hs]i2+3): Ensure operating on REG.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@13637 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 244d43a..a45aeab 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1,5 +1,5 @@
 ;; GCC machine description for Intel X86.
-;; Copyright (C) 1988, 1994, 1995, 1996 Free Software Foundation, Inc.
+;; Copyright (C) 1988, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
 ;; Mostly by William Schelter.
 
 ;; This file is part of GNU CC.
@@ -1898,13 +1898,18 @@
 (define_split
   [(set (match_operand:HI 0 "register_operand" "")
        (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && REGNO (operands[0]) != REGNO (operands[1])"
+ "reload_completed && TARGET_ZERO_EXTEND_WITH_AND"
  [(set (match_dup 0)
        (match_dup 2))
   (set (match_dup 0)
        (and:HI (match_dup 0)
               (const_int 255)))]
- "operands[2] = gen_rtx (REG, HImode, REGNO (operands[1]));")
+ "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0)
+    operands[1] = SUBREG_REG (operands[1]);
+  if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG
+      || REGNO (operands[0]) == REGNO (operands[1]))
+    FAIL;
+  operands[2] = gen_rtx (REG, HImode, REGNO (operands[1]));")
 
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=q,&q,?r")
@@ -1984,13 +1989,18 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
        (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
- "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && REGNO (operands[0]) != REGNO (operands[1])"
+ "reload_completed && TARGET_ZERO_EXTEND_WITH_AND"
  [(set (match_dup 0)
        (match_dup 2))
   (set (match_dup 0)
        (and:SI (match_dup 0)
               (const_int 255)))]
- "operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]));")
+ "if (GET_CODE (operands[1]) == SUBREG && SUBREG_WORD (operands[1]) == 0)
+    operands[1] = SUBREG_REG (operands[1]);
+  if (GET_CODE (operands[1]) != REG
+      || REGNO (operands[0]) == REGNO (operands[1]))
+    FAIL;
+  operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]));")
 
 (define_insn "zero_extendsidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?m")