2001-12-11 Richard Henderson <rth@redhat.com>
+ * config/alpha/alpha.h (TARGET_FIXUP_EV5_PREFETCH): New.
+ * config/alpha/linux.h (TARGET_FIXUP_EV5_PREFETCH): New.
+ * config/alpha/alpha.md (prefetch): New.
+
+2001-12-11 Richard Henderson <rth@redhat.com>
+
* combine.c (simplify_and_const_int): Simplify (AND (PLUS X Y) C)
if C has only low bits set and doesn't intersect with X or Y.
#ifndef TARGET_LD_BUGGY_LDGP
#define TARGET_LD_BUGGY_LDGP 0
#endif
+#ifndef TARGET_FIXUP_EV5_PREFETCH
+#define TARGET_FIXUP_EV5_PREFETCH 0
+#endif
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
[(set_attr "length" "16")
(set_attr "type" "multi")])
+;; Prefetch data.
+;;
+;; On EV4, these instructions are nops -- no load occurs.
+;;
+;; On EV5, these instructions act as a normal load, and thus can trap
+;; if the address is invalid. The OS may (or may not) handle this in
+;; the entMM fault handler and suppress the fault. If so, then this
+;; has the effect of a read prefetch instruction.
+;;
+;; On EV6, these become official prefetch instructions.
+
+(define_insn "prefetch"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (match_operand:DI 1 "const_int_operand" "n")
+ (match_operand:DI 2 "const_int_operand" "n"))]
+ "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
+{
+ /* Interpret "no temporal locality" as this data should be evicted once
+ it is used. The "evict next" alternatives load the data into the cache
+ and leave the LRU eviction counter pointing to that block. */
+ static const char * const alt[2][2] = {
+ {
+ "lds $f31,%a0", /* read, evict next */
+ "ldl $31,%a0", /* read, evict last */
+ },
+ {
+ "ldt $f31,%a0", /* write, evict next */
+ "ldq $31,%a0", /* write, evict last */
+ }
+ };
+
+ bool write = INTVAL (operands[1]) != 0;
+ bool lru = INTVAL (operands[2]) != 0;
+
+ return alt[write][lru];
+}
+ [(set_attr "type" "ild")])
+
;; Close the trap shadow of preceding instructions. This is generated
;; by alpha_reorg.