+Mon Aug 2 16:15:57 1999 David Edelsohn <edelsohn@gnu.org>
+
+ * rs6000/aix43.h (SUBTARGET_SWITCHES): Use -m64 and -m32 instead of
+ -maix64 and -maix32.
+ (ASM_SPEC, ASM_CPU_SPEC, CPP_SPEC, CPP_CPU_SPEC, LIB_SPEC,
+ LINK_SPEC): Change appropriately.
+ * rs6000/rs6000.c (short_cint_operand): Use CONST_OK_FOR_LETTER_P.
+ (u_short_cint_operand): Likewise.
+ * rs6000/rs6000.md (movdi splitters): Add TARGET_POWERPC64 support
+ for 64-bit hosts.
+ * rs6000/t-aix43 (MULTILIB): Change to -m64.
+
+ * invoke.texi (RS/6000 Submodel): Document 64-bit processor options.
+
+Mon Aug 2 16:15:57 1999 Geoff Keating <geoffk@cygnus.com>
+
+ * rs6000/rs6000.c (num_insns_constant_wide): Correct
+ for type promotion.
+ (add_operand): Get test correct for 64-bit HOST_WIDE_INT.
+ (non_add_cint_operand): Likewise.
+ (logical_operand): Likewise.
+ (non_logical_cint_operand): Likewise.
+ (print_operand): Correct printf()s for 64-bit HOST_WIDE_INT.
+ (print_operand_address): Correct printf() for 64-bit HOST_WIDE_INT.
+ (rs6000_select_rtx_section): Suppress warning.
+ (small_data_operand): Suppress warning.
+ (rs6000_got_register): Suppress warning.
+ * rs6000/rs6000.md (andsi3): HOST_WIDE_INT is a signed
+ type, so `J' is generally the wrong constraint for a SImode value;
+ use `L' instead.
+ (andsi3_internal2): Likewise.
+ (andsi3_internal3): Likewise.
+ (iorsi3_internal1): Likewise.
+ (xorsi3_internal1): Likewise.
+ (movsi): Likewise.
+ (movsf_softfloat): Likewise.
+ (scc insns): Likewise.
+ (movsi+2): Preserve sign bits of SImode constant.
+ (floatsidf2_internal+1): Sign-extend SImode constant correctly.
+ (movdf+1): Sign-extend properly.
+ (movdi_32+1): Sign-extend properly.
+ (scc insns): Sign-extend properly.
+
+ * md.texi (RS/6000 EXTRA_CONSTRAINTS): Update documentation for J,
+ K, L, and T.
+
1999-08-02 Richard Henderson <rth@cygnus.com>
* alpha.c (override_options): Move ev6 alpha_tp frobbing out of
#define TARGET_XL_CALL (target_flags & MASK_XL_CALL)
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
- {"aix64", MASK_64BIT | MASK_POWERPC64 | MASK_POWERPC}, \
- {"aix32", - (MASK_64BIT | MASK_POWERPC64)}, \
+ {"64", MASK_64BIT | MASK_POWERPC64 | MASK_POWERPC}, \
+ {"32", - (MASK_64BIT | MASK_POWERPC64)}, \
{"xl-call", MASK_XL_CALL}, \
{"no-xl-call", - MASK_XL_CALL}, \
{"threads", 0}, \
if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \
{ \
target_flags &= ~NON_POWERPC_MASKS; \
- warning ("-maix64 and POWER architecture are incompatible."); \
+ warning ("-m64 and POWER architecture are incompatible."); \
} \
if (TARGET_64BIT && ! (target_flags & MASK_POWERPC64)) \
{ \
target_flags |= MASK_POWERPC64; \
- warning ("-maix64 requires PowerPC64 architecture remain enabled."); \
+ warning ("-m64 requires PowerPC64 architecture remain enabled."); \
} \
} while (0);
#include "rs6000/rs6000.h"
#undef ASM_SPEC
-#define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)"
+#define ASM_SPEC "-u %{m64:-a64 -mppc64} %(asm_cpu)"
/* Common ASM definitions used by ASM_SPEC amonst the various targets
for handling -mcpu=xxx switches. */
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
-"%{!mcpu*: %{!maix64: \
+"%{!mcpu*: %{!m64: \
%{mpower: %{!mpower2: -mpwr}} \
%{mpower2: -mpwr2} \
%{mpowerpc*: %{!mpowerpc64: -mppc}} \
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\
- %{maix64: -D__64BIT__ -D_ARCH_PPC}\
+ %{m64: -D__64BIT__ -D_ARCH_PPC}\
%{mpe: -I/usr/lpp/ppe.poe/include}\
%{mthreads: -D_THREAD_SAFE}\
%(cpp_cpu)"
for handling -mcpu=xxx switches. */
#undef CPP_CPU_SPEC
#define CPP_CPU_SPEC \
-"%{!mcpu*: %{!maix64: \
+"%{!mcpu*: %{!m64: \
%{mpower: %{!mpower2: -D_ARCH_PWR}} \
%{mpower2: -D_ARCH_PWR2} \
%{mpowerpc*: -D_ARCH_PPC} \
#undef LIB_SPEC
#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\
%{p:-L/lib/profiled -L/usr/lib/profiled}\
- %{!maix64:%{!shared:%{g*:-lg}}}\
+ %{!m64:%{!shared:%{g*:-lg}}}\
%{mpe:-L/usr/lpp/ppe.poe/lib -lmpi -lvtd}\
%{mthreads:-L/usr/lib/threads -lpthreads -lc_r /usr/lib/libc.a}\
%{!mthreads:-lc}"
#undef LINK_SPEC
#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
- %{static:-bnso %(link_syscalls) } %{!maix64:%{!shared:%{g*: %(link_libg) }}}\
- %{shared:-bM:SRE %{!e:-bnoentry}} %{maix64:-b64}"
+ %{static:-bnso %(link_syscalls) } %{!m64:%{!shared:%{g*: %(link_libg) }}}\
+ %{shared:-bM:SRE %{!e:-bnoentry}} %{m64:-b64}"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:\
%{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\
%{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\
%{!mpe:\
- %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
- %{!maix64:\
+ %{m64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
+ %{!m64:\
%{mthreads:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
%{!mthreads:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}}"
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
- return ((GET_CODE (op) == CONST_INT
- && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) < 0x10000));
+ return (GET_CODE (op) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
}
/* Similar for a unsigned D field. */
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0);
+ && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'));
}
/* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
HOST_WIDE_INT value;
{
/* signed constant loadable with {cal|addi} */
- if (((unsigned HOST_WIDE_INT)value + 0x8000) < 0x10000)
- return 1;
-
-#if HOST_BITS_PER_WIDE_INT == 32
- /* constant loadable with {cau|addis} */
- else if ((value & 0xffff) == 0)
+ if (CONST_OK_FOR_LETTER_P (value, 'I'))
return 1;
-#else
/* constant loadable with {cau|addis} */
- else if ((value & 0xffff) == 0 && (value & ~0xffffffff) == 0)
+ else if (CONST_OK_FOR_LETTER_P (value, 'L'))
return 1;
+#if HOST_BITS_PER_WIDE_INT == 64
else if (TARGET_64BIT)
{
HOST_WIDE_INT low = value & 0xffffffff;
}
/* Return 1 if the operand is either a non-special register or an item
- that can be used as the operand of an SI add insn. */
+ that can be used as the operand of a `mode' add insn. */
int
add_operand (op, mode)
{
return (reg_or_short_operand (op, mode)
|| (GET_CODE (op) == CONST_INT
- && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0));
+ && CONST_OK_FOR_LETTER_P (INTVAL(op), 'L')));
}
/* Return 1 if OP is a constant but not a valid add_operand. */
{
return (GET_CODE (op) == CONST_INT
&& (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000
- && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
+ && ! CONST_OK_FOR_LETTER_P (INTVAL(op), 'L'));
}
/* Return 1 if the operand is a non-special register or a constant that
{
return (gpc_reg_operand (op, mode)
|| (GET_CODE (op) == CONST_INT
- && ((INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) == 0
- || (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
+ && ((INTVAL (op) & GET_MODE_MASK (mode)
+ & (~ (HOST_WIDE_INT) 0xffff)) == 0
+ || (INTVAL (op) & GET_MODE_MASK (mode)
+ & (~ (HOST_WIDE_INT) 0xffff0000)) == 0)));
}
/* Return 1 if C is a constant that is not a logical operand (as
int
non_logical_cint_operand (op, mode)
register rtx op;
- enum machine_mode mode ATTRIBUTE_UNUSED;
+ enum machine_mode mode;
{
return (GET_CODE (op) == CONST_INT
- && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff)) != 0
- && (INTVAL (op) & (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
+ && (INTVAL (op) & GET_MODE_MASK (mode) &
+ (~ (HOST_WIDE_INT) 0xffff)) != 0
+ && (INTVAL (op) & GET_MODE_MASK (mode) &
+ (~ (HOST_WIDE_INT) 0xffff0000)) != 0);
}
/* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
enum machine_mode mode ATTRIBUTE_UNUSED;
{
#if TARGET_ELF
- rtx sym_ref, const_part;
+ rtx sym_ref;
if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
return 0;
struct rtx_def *
rs6000_got_register (value)
- rtx value;
+ rtx value ATTRIBUTE_UNUSED;
{
/* The second flow pass currently (June 1999) can't update regs_ever_live
without disturbing other parts of the compiler, so update it here to
if (! INT_P (x))
output_operand_lossage ("invalid %%b value");
- fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
return;
case 'B':
/* If constant, output low-order five bits. Otherwise,
write normally. */
if (INT_P (x))
- fprintf (file, "%d", INT_LOWPART (x) & 31);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
else
print_operand (file, x, 0);
return;
/* If constant, output low-order six bits. Otherwise,
write normally. */
if (INT_P (x))
- fprintf (file, "%d", INT_LOWPART (x) & 63);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
else
print_operand (file, x, 0);
return;
if (! INT_P (x))
output_operand_lossage ("invalid %%k value");
- fprintf (file, "%d", ~ INT_LOWPART (x));
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
return;
case 'L':
if (! INT_P (x))
output_operand_lossage ("invalid %%s value");
- fprintf (file, "%d", (32 - INT_LOWPART (x)) & 31);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
return;
case 'S':
if (! INT_P (x))
output_operand_lossage ("invalid %%u value");
- fprintf (file, "0x%x", (INT_LOWPART (x) >> 16) & 0xffff);
+ fprintf (file, HOST_WIDE_INT_PRINT_HEX,
+ (INT_LOWPART (x) >> 16) & 0xffff);
return;
case 'v':
/* If constant, low-order 16 bits of constant, signed. Otherwise, write
normally. */
if (INT_P (x))
- fprintf (file, "%d", ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
else
print_operand (file, x, 0);
return;
/* If constant, low-order 16 bits of constant, unsigned.
Otherwise, write normally. */
if (INT_P (x))
- fprintf (file, "%d", INT_LOWPART (x) & 0xffff);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
else
print_operand (file, x, 0);
return;
reg_names[ REGNO (XEXP (x, 1)) ]);
}
else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
- fprintf (file, "%d(%s)", INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
+ {
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (x, 1)));
+ fprintf (file, "(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
+ }
#if TARGET_ELF
else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
&& CONSTANT_P (XEXP (x, 1)))
void
rs6000_select_rtx_section (mode, x)
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
rtx x;
{
if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x))
if ((size > 0 && size <= g_switch_value)
|| (name
- && ((len == sizeof (".sdata")-1
+ && ((len == sizeof (".sdata") - 1
&& strcmp (name, ".sdata") == 0)
- || (len == sizeof (".sdata2")-1
+ || (len == sizeof (".sdata2") - 1
&& strcmp (name, ".sdata2") == 0)
- || (len == sizeof (".sbss")-1
+ || (len == sizeof (".sbss") - 1
&& strcmp (name, ".sbss") == 0)
- || (len == sizeof (".sbss2")-1
+ || (len == sizeof (".sbss2") - 1
&& strcmp (name, ".sbss2") == 0)
- || (len == sizeof (".PPC.EMB.sdata0")-1
+ || (len == sizeof (".PPC.EMB.sdata0") - 1
&& strcmp (name, ".PPC.EMB.sdata0") == 0)
- || (len == sizeof (".PPC.EMB.sbss0")-1
+ || (len == sizeof (".PPC.EMB.sbss0") - 1
&& strcmp (name, ".PPC.EMB.sbss0") == 0))))
{
rtx sym_ref = XEXP (DECL_RTL (decl), 0);
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:SI 2 "and_operand" "?r,T,K,J")))
+ (match_operand:SI 2 "and_operand" "?r,T,K,L")))
(clobber (match_scratch:CC 3 "=X,X,x,x"))]
""
"@
(define_insn "*andsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
+ (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
(define_insn "*andsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
+ (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
(and:SI (match_dup 1)
(define_insn "*iorsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:SI 2 "logical_operand" "r,K,J")))]
+ (match_operand:SI 2 "logical_operand" "r,K,L")))]
""
"@
or %0,%1,%2
(define_insn "*xorsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
- (match_operand:SI 2 "logical_operand" "r,K,J")))]
+ (match_operand:SI 2 "logical_operand" "r,K,L")))]
""
"@
xor %0,%1,%2
(match_dup 3)))]
"
{
- operands[6] = GEN_INT (0x80000000);
+ operands[6] = GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff);
operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
}")
(match_dup 3)))]
"
{
- operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
+ operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
}")
"
{
int endian = (WORDS_BIG_ENDIAN == 0);
+ HOST_WIDE_INT value = INTVAL (operands[1]);
+
operands[2] = operand_subword (operands[0], endian, 0, DFmode);
operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
- operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+#if HOST_BITS_PER_WIDE_INT == 32
+ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
+#else
+ operands[4] = GEN_INT (value >> 32);
+ operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
+#endif
}")
(define_split
(set (match_dup 3) (match_dup 1))]
"
{
+ HOST_WIDE_INT value = INTVAL (operands[1]);
operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
#if HOST_BITS_PER_WIDE_INT == 32
- operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
#else
- operands[4] = GEN_INT ((HOST_WIDE_INT) INTVAL (operands[1]) >> 32);
- operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffffffff);
+ operands[4] = GEN_INT (value >> 32);
+ operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
#endif
}")
[(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
+;; immediate value valid for a single instruction hiding in a const_double
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(match_operand:DI 1 "const_double_operand" "F"))]
- "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE
+ "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
+ && GET_CODE (operands[1]) == CONST_DOUBLE
&& num_insns_constant (operands[1], DImode) == 1"
"*
{
? \"li %0,%1\" : \"lis %0,%v1\";
}")
+;; sign-extended 32-bit value
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_int_operand" ""))]
&& GET_CODE (operands[1]) == CONST_DOUBLE
&& ((CONST_DOUBLE_HIGH (operands[1]) == 0
&& (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
- || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff
+ || (CONST_DOUBLE_HIGH (operands[1]) == -1
&& (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
[(set (match_dup 0)
(match_dup 2))
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
+ && GET_CODE (operands[1]) == CONST_INT
+ && (((INTVAL (operands[1]) >> 32) == 0
+ && (INTVAL (operands[1]) & 0x80000000) == 0)
+ || ((INTVAL (operands[1]) >> 32) == -1
+ && (INTVAL (operands[1]) & 0x80000000) != 0))
+ && num_insns_constant (operands[1], DImode) > 1"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 3)))]
+ "
+{
+ operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
+ operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
+}")
+
+;; zero-extended 32-bit value
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_double_operand" ""))]
"HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
&& GET_CODE (operands[1]) == CONST_DOUBLE
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
+ && GET_CODE (operands[1]) == CONST_INT
+ && INTVAL (operands[1]) >> 32 == 0
+ && (INTVAL (operands[1]) & 0x80000000) != 0
+ && num_insns_constant (operands[1], DImode) > 1"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (zero_extend:DI (subreg:SI (match_dup 0) 0)))]
+ "
+{ operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32); }")
+
+;; 32-bit value in upper half of doubleword
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_double_operand" ""))]
"HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
&& GET_CODE (operands[1]) == CONST_DOUBLE
"
{ operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
+ && GET_CODE (operands[1]) == CONST_INT
+ && INTVAL (operands[1]) & 0xffffffff == 0"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0)
+ (const_int 32)))]
+ "
+{ operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); }")
+
;; Generate all one-bits and clear left or right.
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
(define_split
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "const_double_operand" ""))]
- "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
+ "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
+ && num_insns_constant (operands[1], DImode) > 1"
[(set (match_dup 0)
(match_dup 2))
(set (match_dup 0)
(match_dup 3)))]
"
{
- HOST_WIDE_INT low;
- HOST_WIDE_INT high;
-
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
- low = CONST_DOUBLE_LOW (operands[1]);
- high = CONST_DOUBLE_HIGH (operands[1]);
+ operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+ operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}
else
-#if HOST_BITS_PER_WIDE_INT == 32
- {
- low = INTVAL (operands[1]);
- high = (low < 0) ? ~0 : 0;
- }
-#else
{
- low = INTVAL (operands[1]) & 0xffffffff;
- high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
+ HOST_WIDE_INT value = INTVAL (operands[1]);
+ operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
+ operands[3] = operands[1];
}
-#endif
+}")
- operands[2] = GEN_INT (high);
- operands[3] = GEN_INT (low);
+(define_split
+ [(set (match_operand:DI 0 "gpc_reg_operand" "")
+ (match_operand:DI 1 "const_int_operand" ""))]
+ "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
+ && num_insns_constant (operands[1], DImode) > 1"
+ [(set (match_dup 0)
+ (match_dup 2))
+ (set (match_dup 0)
+ (ashift:DI (match_dup 0)
+ (const_int 32)))
+ (set (match_dup 0)
+ (ior:DI (match_dup 0)
+ (match_dup 3)))]
+ "
+{
+ HOST_WIDE_INT value = INTVAL (operands[1]);
+ operands[2] = GEN_INT (value >> 32);
+ operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
}")
(define_insn ""
sign-extended to 16 bits. Then see what constant could be XOR'ed
with C to get the sign-extended value. */
- int c = INTVAL (operands[2]);
- int sextc = (c << 16) >> 16;
- int xorv = c ^ sextc;
+ HOST_WIDE_INT c = INTVAL (operands[2]);
+ HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
+ HOST_WIDE_INT xorv = c ^ sextc;
operands[4] = GEN_INT (xorv);
operands[5] = GEN_INT (sextc);
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
(clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
""
"@
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
(compare:CC
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(eq:SI (match_dup 1) (match_dup 2)))
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
""
(compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
(compare:CC
(plus:SI
(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
(match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
- (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
+ (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
""
"@
xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
# different processor models
MULTILIB_OPTIONS = msoft-float \
- mcpu=common/mcpu=power/mcpu=powerpc/maix64
+ mcpu=common/mcpu=power/mcpu=powerpc/m64
MULTILIB_DIRNAMES = soft-float \
- common power powerpc aix64
+ common power powerpc ppc64
MULTILIB_MATCHES = msoft-float=mcpu?403 \
- maix64=maix64 \
mcpu?power=mpower \
mcpu?power=mrios1 \
mcpu?power=mcpu?rios1 \
mcpu?power=mpower2 \
mcpu?power=mrios2 \
mcpu?power=mcpu=rios2 \
+ mcpu?powerpc=mcpu?rs64a \
mcpu?powerpc=mcpu?601 \
mcpu?powerpc=mcpu?602 \
mcpu?powerpc=mcpu?603 \
mcpu?powerpc=mcpu?603e \
mcpu?powerpc=mcpu?604 \
mcpu?powerpc=mcpu?620 \
+ mcpu?powerpc=mcpu?630 \
+ mcpu?powerpc=mcpu?750 \
mcpu?powerpc=mcpu?403 \
mcpu?powerpc=mpowerpc \
mcpu?powerpc=mpowerpc-gpopt \
-mcpu=@var{cpu type}
-mtune=@var{cpu type}
-mpower -mno-power -mpower2 -mno-power2
--mpowerpc -mno-powerpc
+-mpowerpc -mpowerpc64 -mno-powerpc
-mpowerpc-gpopt -mno-powerpc-gpopt
-mpowerpc-gfxopt -mno-powerpc-gfxopt
-mnew-mnemonics -mno-new-mnemonics
-mfull-toc -mminimal-toc -mno-fop-in-toc -mno-sum-in-toc
--maix64 -maix32 -mxl-call -mno-xl-call -mthreads -mpe
+-m64 -m32 -mxl-call -mno-xl-call -mthreads -mpe
-msoft-float -mhard-float -mmultiple -mno-multiple
-mstring -mno-string -mupdate -mno-update
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align
@kindex -mcpu
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type @var{cpu_type}.
-Supported values for @var{cpu_type} are @samp{rs6000}, @samp{rios1},
-@samp{rios2}, @samp{rsc}, @samp{601}, @samp{602}, @samp{603},
-@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{740},
-@samp{750}, @samp{power}, @samp{power2}, @samp{powerpc}, @samp{403},
-@samp{505}, @samp{801}, @samp{821}, @samp{823}, and @samp{860} and
-@samp{common}. @samp{-mcpu=power}, @samp{-mcpu=power2}, and
-@samp{-mcpu=powerpc} specify generic POWER, POWER2 and pure PowerPC
-(i.e., not MPC601) architecture machine types, with an appropriate,
+Supported values for @var{cpu_type} are @samp{rios}, @samp{rios1},
+@samp{rsc}, @samp{rios2}, @samp{rs64a}, @samp{601}, @samp{602},
+@samp{603}, @samp{603e}, @samp{604}, @samp{604e}, @samp{620},
+@samp{630}, @samp{740}, @samp{750}, @samp{power}, @samp{power2},
+@samp{powerpc}, @samp{403}, @samp{505}, @samp{801}, @samp{821},
+@samp{823}, and @samp{860} and @samp{common}. @samp{-mcpu=power},
+@samp{-mcpu=power2}, @samp{-mcpu=powerpc}, and @samp{-mcpu=powerpc64}
+specify generic POWER, POWER2, pure 32-bit PowerPC (i.e., not MPC601),
+and 64-bit PowerPC architecture machine types, with an appropriate,
generic processor model assumed for scheduling purposes.@refill
-@c overfull hbox here --bob 22 jul96
-@c original text between ignore ... end ignore
-@ignore
-Specifying any of the @samp{-mcpu=rios1}, @samp{-mcpu=rios2},
-@samp{-mcpu=rsc}, @samp{-mcpu=power}, or @samp{-mcpu=power2} options
-enables the @samp{-mpower} option and disables the @samp{-mpowerpc}
-option; @samp{-mcpu=601} enables both the @samp{-mpower} and
-@samp{-mpowerpc} options; all of @samp{-mcpu=602}, @samp{-mcpu=603},
-@samp{-mcpu=603e}, @samp{-mcpu=604}, @samp{-mcpu=604e},
-@samp{-mcpu=620}, @samp{-mcpu=403}, @samp{-mcpu=505}, @samp{-mcpu=801},
-@samp{-mcpu=821}, @samp{-mcpu=823}, @samp{-mcpu=860} and
-@samp{-mcpu=powerpc} enable the @samp{-mpowerpc} option and disable the
-@samp{-mpower} option; @samp{-mcpu=common} disables both the
-@samp{-mpower} and @samp{-mpowerpc} options.@refill
-@end ignore
-@c changed paragraph
Specifying any of the following options:
@samp{-mcpu=rios1}, @samp{-mcpu=rios2}, @samp{-mcpu=rsc},
@samp{-mcpu=power}, or @samp{-mcpu=power2}
enables the @samp{-mpower} option and disables the @samp{-mpowerpc} option;
@samp{-mcpu=601} enables both the @samp{-mpower} and @samp{-mpowerpc} options.
-All of @samp{-mcpu=602}, @samp{-mcpu=603}, @samp{-mcpu=603e},
-@samp{-mcpu=604}, @samp{-mcpu=620},
+All of @samp{-mcpu=rs64a}, @samp{-mcpu=602}, @samp{-mcpu=603},
+@samp{-mcpu=603e}, @samp{-mcpu=604}, @samp{-mcpu=620}, @samp{-mcpu=630},
+@samp{-mcpu=740}, and @samp{-mcpu=750}
enable the @samp{-mpowerpc} option and disable the @samp{-mpower} option.
Exactly similarly, all of @samp{-mcpu=403},
@samp{-mcpu=505}, @samp{-mcpu=821}, @samp{-mcpu=860} and @samp{-mcpu=powerpc}
enable the @samp{-mpowerpc} option and disable the @samp{-mpower} option.
@samp{-mcpu=common} disables both the
@samp{-mpower} and @samp{-mpowerpc} options.@refill
-@c end changes to prevent overfull hboxes
AIX versions 4 or greater selects @samp{-mcpu=common} by default, so
-that code will operate on all members of the RS/6000 and PowerPC
+that code will operate on all members of the RS/6000 POWER and PowerPC
families. In that case, GNU CC will use only the instructions in the
common subset of both architectures plus some special AIX common-mode
calls, and will not use the MQ register. GNU CC assumes a generic
@samp{-mcpu=rsc}, @samp{-mcpu=power}, or @samp{-mcpu=power2} also
disables the @samp{new-mnemonics} option. Specifying @samp{-mcpu=601},
@samp{-mcpu=602}, @samp{-mcpu=603}, @samp{-mcpu=603e}, @samp{-mcpu=604},
-@samp{620}, @samp{403}, or @samp{-mcpu=powerpc} also enables the
-@samp{new-mnemonics} option.@refill
+@samp{-mcpu=620}, @samp{-mcpu=630}, @samp{-mcpu=403}, @samp{-mcpu=505},
+@samp{-mcpu=821}, @samp{-mcpu=860} or @samp{-mcpu=powerpc} also enables
+the @samp{new-mnemonics} option.@refill
Specifying @samp{-mcpu=403}, @samp{-mcpu=821}, or @samp{-mcpu=860} also
enables the @samp{-msoft-float} option.
uses extremely little TOC space. You may wish to use this option
only on files that contain less frequently executed code. @refill
-@item -maix64
-@itemx -maix32
-@kindex -maix64
-@kindex -maix32
-Enable AIX 64-bit ABI and calling convention: 64-bit pointers, 64-bit
+@item -m64
+@itemx -m32
+@kindex -m64
+@kindex -m32
+Enable 64-bit PowerPC ABI and calling convention: 64-bit pointers, 64-bit
@code{long} type, and the infrastructure needed to support them.
-Specifying @samp{-maix64} implies @samp{-mpowerpc64} and
-@samp{-mpowerpc}, while @samp{-maix32} disables the 64-bit ABI and
-implies @samp{-mno-powerpc64}. GNU CC defaults to @samp{-maix32}.
+Specifying @samp{-m64} implies @samp{-mpowerpc64} and
+@samp{-mpowerpc}, while @samp{-m32} disables the 64-bit ABI and
+implies @samp{-mno-powerpc64}. GNU CC defaults to @samp{-m32}.
@item -mxl-call
@itemx -mno-xl-call
Signed 16 bit constant
@item J
-Constant whose low 16 bits are 0
+Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
+@code{SImode} constants)
@item K
-Constant whose high 16 bits are 0
+Unsigned 16 bit constant
@item L
-Constant suitable as a mask operand
+Signed 16 bit constant shifted left 16 bits
@item M
Constant larger than 31
@item S
Constant suitable as a 64-bit mask operand
+@item T
+Constant suitable as a 32-bit mask operand
+
@item U
System V Release 4 small data area reference
@end table
OSDN Git Service
