2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.target/arm/combine-cmp-shift.c: New test.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_select_cc_mode): Handle subreg.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@151050
138bc75d-0d04-0410-961f-
82ee72b054a4
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ * config/arm/arm.c (arm_select_cc_mode): Handle subreg.
+
+2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
* config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable.
(*arm_movdf_vfp): Likewise.
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
- if (GET_MODE (y) == SImode && GET_CODE (y) == REG
+ if (GET_MODE (y) == SImode
+ && (REG_P (y) || (GET_CODE (y) == SUBREG))
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
|| GET_CODE (x) == ROTATERT))
/* This operation is performed swapped, but since we only rely on the Z
flag we don't need an additional mode. */
- if (GET_MODE (y) == SImode && REG_P (y)
+ if (GET_MODE (y) == SImode
+ && (REG_P (y) || (GET_CODE (y) == SUBREG))
&& GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_Zmode;
+2009-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * gcc.target/arm/combine-cmp-shift.c: New test.
+
2009-08-24 Kai Tietz <kai.tietz@onevision.com>
*gcc.dg/format/ms-format1.c: Add new cases for I32
--- /dev/null
+/* { dg-options "-O2 -mcpu=cortex-a8" } */
+/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+void abort (void);
+
+SItype
+__mulvsi3 (SItype a, SItype b)
+{
+ const DItype w = (DItype) a * (DItype) b;
+ if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1))
+ abort ();
+ return w;
+}