/* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
- Copyright (C) 1988, 1990, 1991, 1992 Free Software Foundation, Inc.
+ Copyright (C) 1988, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@nyu.edu)
This file is part of GNU CC.
{"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE, \
LABEL_REF, SYMBOL_REF}}, \
{"shift_constant_operand", {CONST_INT, ASHIFT}}, \
- {"const_0__operand", {CONST_INT, ASHIFT}}, \
- {"const_8__operand", {CONST_INT, ASHIFT}}, \
- {"const_16__operand", {CONST_INT, ASHIFT}}, \
- {"const_24__operand", {CONST_INT, ASHIFT}}, \
+ {"const_0_operand", {CONST_INT, ASHIFT}}, \
+ {"const_8_operand", {CONST_INT, ASHIFT}}, \
+ {"const_16_operand", {CONST_INT, ASHIFT}}, \
+ {"const_24_operand", {CONST_INT, ASHIFT}}, \
{"float_const_operand", {CONST_DOUBLE}}, \
{"gpc_reg_operand", {SUBREG, REG}}, \
{"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \
CONST_INT, CONST_DOUBLE}}, \
+ {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT, \
+ CONST_DOUBLE, CONST, \
+ SYMBOL_REF, LABEL_REF}}, \
{"spec_reg_operand", {REG}}, \
{"accum_reg_operand", {REG}}, \
{"srcb_operand", {SUBREG, REG, CONST_INT}}, \
{"reload_memory_operand", {SUBREG, REG, MEM}}, \
{"fp_comparison_operator", {EQ, GT, GE}}, \
{"branch_operator", {GE, LT}}, \
+ {"load_multiple_operation", {PARALLEL}}, \
+ {"store_multiple_operation", {PARALLEL}}, \
{"epilogue_operand", {CODE_LABEL}},
{"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
+ {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
{"fp0_operand", {CONST_DOUBLE}}, \
+ {"current_file_function_operand", {SYMBOL_REF}}, \
{"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
SYMBOL_REF, CONST, LABEL_REF}}, \
{"aligned_memory_operand", {MEM}}, \
Instead, it allows the table built by `genrecog' to be more
compact and efficient, thus speeding up the compiler. The most
important predicates to include in the list specified by this
- macro are thoses used in the most insn patterns.
-
- Note that for the i860 we have one more predicate, i.e.
- `single_insn_src_operand', however this is used only
- infrequently, so we don't put in the PREDICATE_CODES list.
-*/
+ macro are thoses used in the most insn patterns. */
#define PREDICATE_CODES \
{"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
{"logic_const_operand", {CONST_INT}}, \
{"bte_operand", {REG, SUBREG, CONST_INT}}, \
{"indexed_operand", {MEM}}, \
- {"load_operand", {MEM}},
+ {"load_operand", {MEM}}, \
+ {"small_int", {CONST_INT}}, \
+ {"logic_int", {CONST_INT}}, \
+ {"call_insn_operand", {MEM}},
/* Define the information needed to generate branch insns. This is stored
from the compare operation. Note that we can't use "rtx" here since it
/* Definitions of target machine for GNU compiler, for Intel 80960
- Copyright (C) 1992 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993 Free Software Foundation, Inc.
Contributed by Steven McGeady, Intel Corp.
Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
{"eq_or_neq", {EQ, NE}}, \
{"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
CONST_DOUBLE, CONST}}, \
- {"power2_operand", {CONST_INT}},
+ {"power2_operand", {CONST_INT}}, \
+ {"cmplpower2_operand", {CONST_INT}},
/* Define functions in i960.c and used in insn-output.c. */
/* Definitions of target machine for GNU compiler.
Motorola m88100 in an 88open OCS/BCS environment.
- Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
+ Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@mcc.com)
Enhanced by Michael Meissner (meissner@osf.org)
Version 2 port by Tom Wood (Tom_Wood@NeXT.com)
{"add_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_bbx_mask_operand", {SUBREG, REG, CONST_INT}}, \
{"real_or_0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+ {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
{"relop", {EQ, NE, LT, LE, GE, GT, LTU, LEU, GEU, GTU}}, \
{"relop_no_unsigned", {EQ, NE, LT, LE, GE, GT}}, \
{"equality_op", {EQ, NE}}, \
/* Definitions of target machine for GNU compiler. MIPS version.
+ Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr
Changed by Michael Meissner, meissner@osf.org
- Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
This file is part of GNU CC.
{"cmp2_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
LTU, LEU }}, \
{"fcmp_op", { EQ, NE, GT, GE, LT, LE }}, \
+ {"pc_or_label_operand", { PC, LABEL_REF }}, \
+ {"call_insn_operand", { MEM }}, \
{"uns_cmp_op", { GTU, GEU, LTU, LEU }},
\f
{"non_logical_cint_operand", {CONST_INT}}, \
{"mask_operand", {CONST_INT}}, \
{"call_operand", {SYMBOL_REF, REG}}, \
- {"current_file_function_operand", {SYMBOL_REF}}, \
+ {"current_file_function_operand", {SYMBOL_REF}}, \
{"input_operand", {SUBREG, MEM, REG, CONST_INT}}, \
- {"branch_comparison_operation", {EQ, NE, LE, LT, GE, \
- LT, LEU, LTU, GEU, GTU}}, \
- {"scc_comparison_operation", {EQ, NE, LE, LT, GE, \
- LT, LEU, LTU, GEU, GTU}},
+ {"load_multiple_operation", {PARALLEL}}, \
+ {"store_multiple_operation", {PARALLEL}}, \
+ {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
+ LT, LEU, LTU, GEU, GTU}}, \
+ {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
+ LT, LEU, LTU, GEU, GTU}},
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