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2005-05-09 Adrian Straetling <straetling@de.ibm.com>
authoruweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 9 May 2005 17:29:33 +0000 (17:29 +0000)
committeruweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4>
Mon, 9 May 2005 17:29:33 +0000 (17:29 +0000)
* config/s390/s390.md: ("FPR") New mode macro.
("de", "dee"): New mode attributes.
("cmpdf", "cmpsf"): Merge.
("*cmpdf_ccs_0", "*cmpsf_ccs_0"): Merge.
("*cmpdf_ccs_0_ibm", "*cmpdf_ccs_0_ibm"): Merge.
("*cmpdf_ccs", "*cmpsf_ccs"): Merge.
("*cmpdf_ccs_ibm", "*cmpsf_ccs_ibm"): Merge.
("floatdidf2", "floatdisf2"): Merge.
("adddf3", "addsf3"): Merge.
("*adddf3", "*addsf3"): Merge.
("*adddf3_cc", "*addsf3_cc"): Merge.
("*adddf3_cconly", "*addsf3_cconly"): Merge.
("*adddf3_ibm", "*addsf3_ibm"): Merge.
("subdf3", "subsf3"): Merge.
("*subdf3", "*subsf3"): Merge.
("*subdf3_cc", "*subsf3_cc"): Merge.
("*subdf3_cconly", "*subsf3_cconly"): Merge.
("*subdf3_ibm", "*subsf3_ibm"): Merge.
("muldf3", "mulsf3"): Merge.
("*muldf3", "*mulsf3" "): Merge.
("*muldf3_ibm", "*mulsf3_ibm"): Merge.
("*fmadddf", "*fmaddsf"): Merge.
("*fmsubdf", "*fmsubsf"): Merge.
("divdf3", "divsf3"): Merge.
("*divdf3", "*divsf3"): Merge.
("*divdf3_ibm", "*divsf3_ibm"): Merge.
("negdf2", "negsf2"): Merge.
("*negdf2_cc", "*negsf2_cc"): Merge.
("*negdf2_cconly", "*negsf2_cconly"): Merge.
("*negdf2", "*negsf2"): Merge.
("*negdf2_ibm", "*negsf2_ibm"): Merge.
("absdf2", "abssf2"): Merge.
("*absdf2_cc", "*abssf2_cc"): Merge.
("*absdf2_cconly", "*abssf2_cconly"): Merge.
("*absdf2", "*abssf2"): Merge.
("*absdf2_ibm", "*abssf2_ibm"): Merge.
("*negabsdf2_cc", "*negabssf2_cc"): Merge.
("*negabsdf2_cconly", "*negabssf2_cconly"): Merge.
("*negabsdf2", "*negabssf2"): Merge.
("sqrtdf2", "sqrtsf2"): Merge.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99457 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/s390/s390.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fdb1dbc..c3ad2e8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,48 @@
 2005-05-09  Adrian Straetling  <straetling@de.ibm.com>
 
+       * config/s390/s390.md: ("FPR") New mode macro.
+       ("de", "dee"): New mode attributes.
+       ("cmpdf", "cmpsf"): Merge.
+       ("*cmpdf_ccs_0", "*cmpsf_ccs_0"): Merge.
+       ("*cmpdf_ccs_0_ibm", "*cmpdf_ccs_0_ibm"): Merge.
+       ("*cmpdf_ccs", "*cmpsf_ccs"): Merge.
+       ("*cmpdf_ccs_ibm", "*cmpsf_ccs_ibm"): Merge.
+       ("floatdidf2", "floatdisf2"): Merge.
+       ("adddf3", "addsf3"): Merge.
+       ("*adddf3", "*addsf3"): Merge.
+       ("*adddf3_cc", "*addsf3_cc"): Merge.
+       ("*adddf3_cconly", "*addsf3_cconly"): Merge.
+       ("*adddf3_ibm", "*addsf3_ibm"): Merge.
+       ("subdf3", "subsf3"): Merge.
+       ("*subdf3", "*subsf3"): Merge.
+       ("*subdf3_cc", "*subsf3_cc"): Merge.
+       ("*subdf3_cconly", "*subsf3_cconly"): Merge.
+       ("*subdf3_ibm", "*subsf3_ibm"): Merge.
+       ("muldf3", "mulsf3"): Merge.
+       ("*muldf3", "*mulsf3" "): Merge.
+       ("*muldf3_ibm", "*mulsf3_ibm"): Merge.
+       ("*fmadddf", "*fmaddsf"): Merge.
+       ("*fmsubdf", "*fmsubsf"): Merge.
+       ("divdf3", "divsf3"): Merge.
+       ("*divdf3", "*divsf3"): Merge.
+       ("*divdf3_ibm", "*divsf3_ibm"): Merge.
+       ("negdf2", "negsf2"): Merge.
+       ("*negdf2_cc", "*negsf2_cc"): Merge.
+       ("*negdf2_cconly", "*negsf2_cconly"): Merge.
+       ("*negdf2", "*negsf2"): Merge.
+       ("*negdf2_ibm", "*negsf2_ibm"): Merge.
+       ("absdf2", "abssf2"): Merge.
+       ("*absdf2_cc", "*abssf2_cc"): Merge.
+       ("*absdf2_cconly", "*abssf2_cconly"): Merge.
+       ("*absdf2", "*abssf2"): Merge.
+       ("*absdf2_ibm", "*abssf2_ibm"): Merge.
+       ("*negabsdf2_cc", "*negabssf2_cc"): Merge.
+       ("*negabsdf2_cconly", "*negabssf2_cconly"): Merge.
+       ("*negabsdf2", "*negabssf2"): Merge.
+       ("sqrtdf2", "sqrtsf2"): Merge.
+
+2005-05-09  Adrian Straetling  <straetling@de.ibm.com>
+
        * config/s390/s390.c: (s390_adjust_priority): Adapt to changed 
        attribute names.
        * config/s390/2084.md: ("x_fsimpd", "x_fsimps", "x_fdivd", "x_fdivs",
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index ef73692..0c752f5 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -235,6 +235,10 @@
 
 ;; Macros
 
+;; This mode macro allows DF and SF patterns to be generated from the
+;; same template.
+(define_mode_macro FPR     [DF SF])
+
 ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated
 ;; from the same template.
 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
@@ -264,6 +268,14 @@
 (define_code_macro SHIFT [ashift lshiftrt])
 
 
+;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode
+;; and "ltebr" in SFmode.
+(define_mode_attr de [(DF "d") (SF "e")])
+
+;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode
+;; and "meebr" in SFmode.  This is needed for the 'mul<mode>3' pattern. 
+(define_mode_attr dee [(DF "d") (SF "ee")])
+
 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 
 ;; 'ashift' and "srdl" in 'lshiftrt'.
 (define_code_attr lr [(ashift "l") (lshiftrt "r")])
@@ -311,21 +323,10 @@
   DONE;
 })
 
-(define_expand "cmpdf"
-  [(set (reg:CC 33)
-        (compare:CC (match_operand:DF 0 "register_operand" "")
-                    (match_operand:DF 1 "general_operand" "")))]
-  "TARGET_HARD_FLOAT"
-{
-  s390_compare_op0 = operands[0];
-  s390_compare_op1 = operands[1];
-  DONE;
-})
-
-(define_expand "cmpsf"
+(define_expand "cmp<mode>"
   [(set (reg:CC 33)
-        (compare:CC (match_operand:SF 0 "register_operand" "")
-                    (match_operand:SF 1 "general_operand" "")))]
+        (compare:CC (match_operand:FPR 0 "register_operand" "")
+                    (match_operand:FPR 1 "general_operand" "")))]
   "TARGET_HARD_FLOAT"
 {
   s390_compare_op0 = operands[0];
@@ -692,90 +693,47 @@
 })
 
 
-; DF instructions
-
-(define_insn "*cmpdf_ccs_0"
-  [(set (reg 33)
-        (compare (match_operand:DF 0 "register_operand" "f")
-                 (match_operand:DF 1 "const0_operand" "")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ltdbr\t%0,%0"
-   [(set_attr "op_type" "RRE")
-    (set_attr "type"  "fsimpdf")])
-
-(define_insn "*cmpdf_ccs_0_ibm"
-  [(set (reg 33)
-        (compare (match_operand:DF 0 "register_operand" "f")
-                 (match_operand:DF 1 "const0_operand" "")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "ltdr\t%0,%0"
-   [(set_attr "op_type" "RR")
-    (set_attr "type"  "fsimpdf")])
-
-(define_insn "*cmpdf_ccs"
-  [(set (reg 33)
-        (compare (match_operand:DF 0 "register_operand" "f,f")
-                 (match_operand:DF 1 "general_operand" "f,R")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   cdbr\t%0,%1
-   cdb\t%0,%1"
-   [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type"  "fsimpdf")])
-
-(define_insn "*cmpdf_ccs_ibm"
-  [(set (reg 33)
-        (compare (match_operand:DF 0 "register_operand" "f,f")
-                 (match_operand:DF 1 "general_operand" "f,R")))]
-  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   cdr\t%0,%1
-   cd\t%0,%1"
-   [(set_attr "op_type" "RR,RX")
-    (set_attr "type"  "fsimpdf")])
-
-
-; SF instructions
+; (DF|SF) instructions
 
-(define_insn "*cmpsf_ccs_0"
+(define_insn "*cmp<mode>_ccs_0"
   [(set (reg 33)
-        (compare (match_operand:SF 0 "register_operand" "f")
-                 (match_operand:SF 1 "const0_operand" "")))]
+        (compare (match_operand:FPR 0 "register_operand" "f")
+                 (match_operand:FPR 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ltebr\t%0,%0"
+  "lt<de>br\t%0,%0"
    [(set_attr "op_type" "RRE")
-    (set_attr "type"  "fsimpsf")])
+    (set_attr "type"  "fsimp<mode>")])
 
-(define_insn "*cmpsf_ccs_0_ibm"
+(define_insn "*cmp<mode>_ccs_0_ibm"
   [(set (reg 33)
-        (compare (match_operand:SF 0 "register_operand" "f")
-                 (match_operand:SF 1 "const0_operand" "")))]
+        (compare (match_operand:FPR 0 "register_operand" "f")
+                 (match_operand:FPR 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lter\t%0,%0"
+  "lt<de>r\t%0,%0"
    [(set_attr "op_type" "RR")
-    (set_attr "type"  "fsimpsf")])
+    (set_attr "type"  "fsimp<mode>")])
 
-(define_insn "*cmpsf_ccs"
+(define_insn "*cmp<mode>_ccs"
   [(set (reg 33)
-        (compare (match_operand:SF 0 "register_operand" "f,f")
-                 (match_operand:SF 1 "general_operand" "f,R")))]
+        (compare (match_operand:FPR 0 "register_operand" "f,f")
+                 (match_operand:FPR 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   cebr\t%0,%1
-   ceb\t%0,%1"
+   c<de>br\t%0,%1
+   c<de>b\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
-    (set_attr "type"  "fsimpsf")])
+    (set_attr "type"  "fsimp<mode>")])
 
-(define_insn "*cmpsf_ccs"
+(define_insn "*cmp<mode>_ccs_ibm"
   [(set (reg 33)
-        (compare (match_operand:SF 0 "register_operand" "f,f")
-                 (match_operand:SF 1 "general_operand" "f,R")))]
+        (compare (match_operand:FPR 0 "register_operand" "f,f")
+                 (match_operand:FPR 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   cer\t%0,%1
-   ce\t%0,%1"
+   c<de>r\t%0,%1
+   c<de>\t%0,%1"
    [(set_attr "op_type" "RR,RX")
-    (set_attr "type"  "fsimpsf")])
+    (set_attr "type"  "fsimp<mode>")])
 
 
 ;;
@@ -2954,26 +2912,14 @@
    (set_attr "type"    "ftoi")])
 
 ;
-; floatdidf2 instruction pattern(s).
-;
-
-(define_insn "floatdidf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (float:DF (match_operand:DI 1 "register_operand" "d")))]
-  "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cdgbr\t%0,%1"
-  [(set_attr "op_type" "RRE")
-   (set_attr "type"    "itof" )])
-
-;
-; floatdisf2 instruction pattern(s).
+; floatdi(df|sf)2 instruction pattern(s).
 ;
 
-(define_insn "floatdisf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (float:SF (match_operand:DI 1 "register_operand" "d")))]
+(define_insn "floatdi<mode>2"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (float:FPR (match_operand:DI 1 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cegbr\t%0,%1"
+  "c<de>gbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "itof" )])
 
@@ -3514,132 +3460,68 @@
   [(set_attr "op_type"  "RR,RI,RX,RXY")])
 
 ;
-; adddf3 instruction pattern(s).
+; add(df|sf)3 instruction pattern(s).
 ;
 
-(define_expand "adddf3"
+(define_expand "add<mode>3"
   [(parallel
-    [(set (match_operand:DF 0 "register_operand" "=f,f")
-          (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                   (match_operand:DF 2 "general_operand" "f,R")))
+    [(set (match_operand:FPR 0 "register_operand" "=f,f")
+          (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                    (match_operand:FPR 2 "general_operand" "f,R")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:DF 2 "general_operand" "f,R")))
+(define_insn "*add<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:FPR 2 "general_operand" "f,R")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   adbr\t%0,%2
-   adb\t%0,%2"
+   a<de>br\t%0,%2
+   a<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*adddf3_cc"
+(define_insn "*add<mode>3_cc"
   [(set (reg 33)
-       (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DF 2 "general_operand" "f,R"))
-                (match_operand:DF 3 "const0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "=f,f")
-       (plus:DF (match_dup 1) (match_dup 2)))]
+       (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                          (match_operand:FPR 2 "general_operand" "f,R"))
+                (match_operand:FPR 3 "const0_operand" "")))
+   (set (match_operand:FPR 0 "register_operand" "=f,f")
+       (plus:FPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   adbr\t%0,%2
-   adb\t%0,%2"
+   a<de>br\t%0,%2
+   a<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*adddf3_cconly"
+(define_insn "*add<mode>3_cconly"
   [(set (reg 33)
-       (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:DF 2 "general_operand" "f,R"))
-                (match_operand:DF 3 "const0_operand" "")))
-   (clobber (match_scratch:DF 0 "=f,f"))]
+       (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                          (match_operand:FPR 2 "general_operand" "f,R"))
+                (match_operand:FPR 3 "const0_operand" "")))
+   (clobber (match_scratch:FPR 0 "=f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-  adbr\t%0,%2
-  adb\t%0,%2"
+   a<de>br\t%0,%2
+   a<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*adddf3_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:DF 2 "general_operand" "f,R")))
+(define_insn "*add<mode>3_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:FPR 2 "general_operand" "f,R")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   adr\t%0,%2
-   ad\t%0,%2"
+   a<de>r\t%0,%2
+   a<de>\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fsimpdf")])
-
-;
-; addsf3 instruction pattern(s).
-;
-
-(define_expand "addsf3"
-  [(parallel
-    [(set (match_operand:SF 0 "register_operand" "=f,f")
-          (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                   (match_operand:SF 2 "general_operand" "f,R")))
-     (clobber (reg:CC 33))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SF 2 "general_operand" "f,R")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   aebr\t%0,%2
-   aeb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*addsf3_cc"
-  [(set (reg 33)
-       (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:SF 2 "general_operand" "f,R"))
-                (match_operand:SF 3 "const0_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "=f,f")
-       (plus:SF (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   aebr\t%0,%2
-   aeb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*addsf3_cconly"
-  [(set (reg 33)
-       (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                         (match_operand:SF 2 "general_operand" "f,R"))
-                (match_operand:SF 3 "const0_operand" "")))
-   (clobber (match_scratch:SF 0 "=f,f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   aebr\t%0,%2
-   aeb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*addsf3_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SF 2 "general_operand" "f,R")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   aer\t%0,%2
-   ae\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
 
 ;;
@@ -3982,132 +3864,68 @@
 
 
 ;
-; subdf3 instruction pattern(s).
+; sub(df|sf)3 instruction pattern(s).
 ;
 
-(define_expand "subdf3"
+(define_expand "sub<mode>3"
   [(parallel
-    [(set (match_operand:DF 0 "register_operand" "=f,f")
-          (minus:DF (match_operand:DF 1 "register_operand" "0,0")
-                    (match_operand:DF 2 "general_operand" "f,R")))
+    [(set (match_operand:FPR 0 "register_operand" "=f,f")
+          (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                     (match_operand:FPR 2 "general_operand" "f,R")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (minus:DF (match_operand:DF 1 "register_operand" "0,0")
-                  (match_operand:DF 2 "general_operand" "f,R")))
+(define_insn "*sub<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                   (match_operand:FPR 2 "general_operand" "f,R")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sdbr\t%0,%2
-   sdb\t%0,%2"
+   s<de>br\t%0,%2
+   s<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*subdf3_cc"
+(define_insn "*sub<mode>3_cc"
   [(set (reg 33)
-       (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
-                          (match_operand:DF 2 "general_operand" "f,R"))
-                (match_operand:DF 3 "const0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "=f,f")
-       (minus:DF (match_dup 1) (match_dup 2)))]
+       (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+                           (match_operand:FPR 2 "general_operand" "f,R"))
+                (match_operand:FPR 3 "const0_operand" "")))
+   (set (match_operand:FPR 0 "register_operand" "=f,f")
+       (minus:FPR (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sdbr\t%0,%2
-   sdb\t%0,%2"
+   s<de>br\t%0,%2
+   s<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*subdf3_cconly"
+(define_insn "*sub<mode>3_cconly"
   [(set (reg 33)
-       (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
-                          (match_operand:DF 2 "general_operand" "f,R"))
-                (match_operand:DF 3 "const0_operand" "")))
-   (clobber (match_scratch:DF 0 "=f,f"))]
+       (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
+                           (match_operand:FPR 2 "general_operand" "f,R"))
+                (match_operand:FPR 3 "const0_operand" "")))
+   (clobber (match_scratch:FPR 0 "=f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sdbr\t%0,%2
-   sdb\t%0,%2"
+   s<de>br\t%0,%2
+   s<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpdf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*subdf3_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (minus:DF (match_operand:DF 1 "register_operand" "0,0")
-                  (match_operand:DF 2 "general_operand" "f,R")))
+(define_insn "*sub<mode>3_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                   (match_operand:FPR 2 "general_operand" "f,R")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   sdr\t%0,%2
-   sd\t%0,%2"
+   s<de>r\t%0,%2
+   s<de>\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fsimpdf")])
-
-;
-; subsf3 instruction pattern(s).
-;
-
-(define_expand "subsf3"
-  [(parallel
-    [(set (match_operand:SF 0 "register_operand" "=f,f")
-          (minus:SF (match_operand:SF 1 "register_operand" "0,0")
-                    (match_operand:SF 2 "general_operand" "f,R")))
-     (clobber (reg:CC 33))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (minus:SF (match_operand:SF 1 "register_operand" "0,0")
-                  (match_operand:SF 2 "general_operand" "f,R")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   sebr\t%0,%2
-   seb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*subsf3_cc"
-  [(set (reg 33)
-       (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
-                          (match_operand:SF 2 "general_operand" "f,R"))
-                (match_operand:SF 3 "const0_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "=f,f")
-       (minus:SF (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   sebr\t%0,%2
-   seb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*subsf3_cconly"
-  [(set (reg 33)
-       (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
-                          (match_operand:SF 2 "general_operand" "f,R"))
-                (match_operand:SF 3 "const0_operand" "")))
-   (clobber (match_scratch:SF 0 "=f,f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   sebr\t%0,%2
-   seb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fsimpsf")])
-
-(define_insn "*subsf3_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (minus:SF (match_operand:SF 1 "register_operand" "0,0")
-                  (match_operand:SF 2 "general_operand" "f,R")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   ser\t%0,%2
-   se\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
 
 ;;
@@ -4320,118 +4138,61 @@
    (set_attr "type"     "imulsi")])
 
 ;
-; muldf3 instruction pattern(s).
+; mul(df|sf)3 instruction pattern(s).
 ;
 
-(define_expand "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:DF 2 "general_operand" "f,R")))]
+(define_expand "mul<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   mdbr\t%0,%2
-   mdb\t%0,%2"
+   m<dee>br\t%0,%2
+   m<dee>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fmuldf")])
+   (set_attr "type"     "fmul<mode>")])
 
-(define_insn "*muldf3_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*mul<mode>3_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   mdr\t%0,%2
-   md\t%0,%2"
+   m<de>r\t%0,%2
+   m<de>\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"    "fmuldf")])
+   (set_attr "type"     "fmul<mode>")])
 
-(define_insn "*fmadddf"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-       (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
-                         (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
-                (match_operand:DF 3 "register_operand" "0,0")))]
+(define_insn "*fmadd<mode>"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+       (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f")
+                          (match_operand:FPR 2 "nonimmediate_operand"  "f,R"))
+                (match_operand:FPR 3 "register_operand" "0,0")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
   "@
-   madbr\t%0,%1,%2
-   madb\t%0,%1,%2"
+   ma<de>br\t%0,%1,%2
+   ma<de>b\t%0,%1,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type" "fmuldf")])
+   (set_attr "type"     "fmul<mode>")])
 
-(define_insn "*fmsubdf"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-       (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
-                          (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
-                (match_operand:DF 3 "register_operand" "0,0")))]
+(define_insn "*fmsub<mode>"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+       (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f")
+                           (match_operand:FPR 2 "nonimmediate_operand"  "f,R"))
+                (match_operand:FPR 3 "register_operand" "0,0")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
   "@
-   msdbr\t%0,%1,%2
-   msdb\t%0,%1,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type" "fmuldf")])
-
-;
-; mulsf3 instruction pattern(s).
-;
-
-(define_expand "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   meebr\t%0,%2
-   meeb\t%0,%2"
+   ms<de>br\t%0,%1,%2
+   ms<de>b\t%0,%1,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fmulsf")])
-
-(define_insn "*mulsf3_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
-                 (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   mer\t%0,%2
-   me\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fmulsf")])
-
-(define_insn "*fmaddsf"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-       (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
-                         (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
-                (match_operand:SF 3 "register_operand" "0,0")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
-  "@
-   maebr\t%0,%1,%2
-   maeb\t%0,%1,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type" "fmulsf")])
-
-(define_insn "*fmsubsf"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-       (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
-                          (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
-                 (match_operand:SF 3 "register_operand" "0,0")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
-  "@
-   msebr\t%0,%1,%2
-   mseb\t%0,%1,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type" "fmulsf")])
+   (set_attr "type"     "fmul<mode>")])
 
 ;;
 ;;- Divide and modulo instructions.
@@ -4870,70 +4631,37 @@
 })
 
 ;
-; divdf3 instruction pattern(s).
+; div(df|sf)3 instruction pattern(s).
 ;
 
-(define_expand "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (div:DF (match_operand:DF 1 "register_operand" "0,0")
-                (match_operand:DF 2 "general_operand" "f,R")))]
+(define_expand "div<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                 (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (div:DF (match_operand:DF 1 "register_operand" "0,0")
-                (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                 (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   ddbr\t%0,%2
-   ddb\t%0,%2"
+   d<de>br\t%0,%2
+   d<de>b\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fdivdf")])
+   (set_attr "type"     "fdiv<mode>")])
 
-(define_insn "*divdf3_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (div:DF (match_operand:DF 1 "register_operand" "0,0")
-                (match_operand:DF 2 "general_operand" "f,R")))]
+(define_insn "*div<mode>3_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
+                 (match_operand:FPR 2 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   ddr\t%0,%2
-   dd\t%0,%2"
+   d<de>r\t%0,%2
+   d<de>\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fdivdf")])
-
-;
-; divsf3 instruction pattern(s).
-;
-
-(define_expand "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (div:SF (match_operand:SF 1 "register_operand" "0,0")
-                (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (div:SF (match_operand:SF 1 "register_operand" "0,0")
-                (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   debr\t%0,%2
-   deb\t%0,%2"
-  [(set_attr "op_type"  "RRE,RXE")
-   (set_attr "type"     "fdivsf")])
-
-(define_insn "*divsf3_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (div:SF (match_operand:SF 1 "register_operand" "0,0")
-                (match_operand:SF 2 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "@
-   der\t%0,%2
-   de\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
-   (set_attr "type"     "fdivsf")])
+   (set_attr "type"     "fdiv<mode>")])
 
 
 ;;
@@ -5893,106 +5621,55 @@
    operands[6] = gen_label_rtx ();")
 
 ;
-; negdf2 instruction pattern(s).
-;
-
-(define_expand "negdf2"
-  [(parallel
-    [(set (match_operand:DF 0 "register_operand" "=f")
-          (neg:DF (match_operand:DF 1 "register_operand" "f")))
-     (clobber (reg:CC 33))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*negdf2_cc"
-  [(set (reg 33)
-        (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "=f")
-        (neg:DF (match_dup 1)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*negdf2_cconly"
-  [(set (reg 33)
-        (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (clobber (match_scratch:DF 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (neg:DF (match_operand:DF 1 "register_operand" "f")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-
-(define_insn "*negdf2_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (neg:DF (match_operand:DF 1 "register_operand" "f")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lcdr\t%0,%1"
-  [(set_attr "op_type"  "RR")
-   (set_attr "type"     "fsimpdf")])
-
-;
-; negsf2 instruction pattern(s).
+; neg(df|sf)2 instruction pattern(s).
 ;
 
-(define_expand "negsf2"
+(define_expand "neg<mode>2"
   [(parallel
-    [(set (match_operand:SF 0 "register_operand" "=f")
-          (neg:SF (match_operand:SF 1 "register_operand" "f")))
+    [(set (match_operand:FPR 0 "register_operand" "=f")
+          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*negsf2_cc"
+(define_insn "*neg<mode>2_cc"
   [(set (reg 33)
-        (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "=f")
-        (neg:SF (match_dup 1)))]
+        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (set (match_operand:FPR 0 "register_operand" "=f")
+        (neg:FPR (match_dup 1)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcebr\t%0,%1"
+  "lc<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*negsf2_cconly"
+(define_insn "*neg<mode>2_cconly"
   [(set (reg 33)
-        (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (clobber (match_scratch:SF 0 "=f"))]
+        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (clobber (match_scratch:FPR 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcebr\t%0,%1"
+  "lc<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (neg:SF (match_operand:SF 1 "register_operand" "f")))
+(define_insn "*neg<mode>2"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcebr\t%0,%1"
+  "lc<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*negsf2_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (neg:SF (match_operand:SF 1 "register_operand" "f")))
+(define_insn "*neg<mode>2_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lcer\t%0,%1"
+  "lc<de>r\t%0,%1"
   [(set_attr "op_type"  "RR")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
 
 ;;
@@ -6051,106 +5728,55 @@
   [(set_attr "op_type"  "RR<E>")])
 
 ;
-; absdf2 instruction pattern(s).
+; abs(df|sf)2 instruction pattern(s).
 ;
 
-(define_expand "absdf2"
+(define_expand "abs<mode>2"
   [(parallel
-    [(set (match_operand:DF 0 "register_operand" "=f")
-          (abs:DF (match_operand:DF 1 "register_operand" "f")))
+    [(set (match_operand:FPR 0 "register_operand" "=f")
+          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
   "")
 
-(define_insn "*absdf2_cc"
-  [(set (reg 33)
-        (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "=f")
-        (abs:DF (match_dup 1)))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*absdf2_cconly"
-  [(set (reg 33)
-        (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (clobber (match_scratch:DF 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (abs:DF (match_operand:DF 1 "register_operand" "f")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpdbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-
-(define_insn "*absdf2_ibm"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (abs:DF (match_operand:DF 1 "register_operand" "f")))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lpdr\t%0,%1"
-  [(set_attr "op_type"  "RR")
-   (set_attr "type"     "fsimpdf")])
-
-;
-; abssf2 instruction pattern(s).
-;
-
-(define_expand "abssf2"
-  [(parallel
-    [(set (match_operand:SF 0 "register_operand" "=f")
-          (abs:SF (match_operand:SF 1 "register_operand" "f")))
-     (clobber (reg:CC 33))])]
-  "TARGET_HARD_FLOAT"
-  "")
-
-(define_insn "*abssf2_cc"
+(define_insn "*abs<mode>2_cc"
   [(set (reg 33)
-        (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "=f")
-        (abs:SF (match_dup 1)))]
+        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (set (match_operand:FPR 0 "register_operand" "=f")
+        (abs:FPR (match_dup 1)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpebr\t%0,%1"
+  "lp<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*abssf2_cconly"
+(define_insn "*abs<mode>2_cconly"
   [(set (reg 33)
-        (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (clobber (match_scratch:SF 0 "=f"))]
+        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (clobber (match_scratch:FPR 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpebr\t%0,%1"
+  "lp<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (abs:SF (match_operand:SF 1 "register_operand" "f")))
+(define_insn "*abs<mode>2"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpebr\t%0,%1"
+  "lp<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
-(define_insn "*abssf2_ibm"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (abs:SF (match_operand:SF 1 "register_operand" "f")))
+(define_insn "*abs<mode>2_ibm"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lper\t%0,%1"
+  "lp<de>r\t%0,%1"
   [(set_attr "op_type"  "RR")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ;;
 ;;- Negated absolute value instructions
@@ -6212,97 +5838,54 @@
 ; Floating point
 ;
 
-(define_insn "*negabsdf2_cc"
-  [(set (reg 33)
-        (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (set (match_operand:DF 0 "register_operand" "=f")
-        (neg:DF (abs:DF (match_dup 1))))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lndbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*negabsdf2_cconly"
-  [(set (reg 33)
-        (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
-                 (match_operand:DF 2 "const0_operand" "")))
-   (clobber (match_scratch:DF 0 "=f"))]
-  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lndbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-  
-(define_insn "*negabsdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-        (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
-   (clobber (reg:CC 33))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lndbr\t%0,%1"
-  [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpdf")])
-
-(define_insn "*negabssf2_cc"
+(define_insn "*negabs<mode>2_cc"
   [(set (reg 33)
-        (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (set (match_operand:SF 0 "register_operand" "=f")
-        (neg:SF (abs:SF (match_dup 1))))]
+        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (set (match_operand:FPR 0 "register_operand" "=f")
+        (neg:FPR (abs:FPR (match_dup 1))))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lnebr\t%0,%1"
+  "ln<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*negabssf2_cconly"
+(define_insn "*negabs<mode>2_cconly"
   [(set (reg 33)
-        (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
-                 (match_operand:SF 2 "const0_operand" "")))
-   (clobber (match_scratch:SF 0 "=f"))]
+        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+                 (match_operand:FPR 2 "const0_operand" "")))
+   (clobber (match_scratch:FPR 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lnebr\t%0,%1"
+  "ln<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
   
-(define_insn "*negabssf2"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-        (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
+(define_insn "*negabs<mode>2"
+  [(set (match_operand:FPR 0 "register_operand" "=f")
+        (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lnebr\t%0,%1"
+  "ln<de>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
-   (set_attr "type"     "fsimpsf")])
+   (set_attr "type"     "fsimp<mode>")])
 
 ;;
 ;;- Square root instructions.
 ;;
 
 ;
-; sqrtdf2 instruction pattern(s).
+; sqrt(df|sf)2 instruction pattern(s).
 ;
 
-(define_insn "sqrtdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-       (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
+(define_insn "sqrt<mode>2"
+  [(set (match_operand:FPR 0 "register_operand" "=f,f")
+       (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sqdbr\t%0,%1
-   sqdb\t%0,%1"
+   sq<de>br\t%0,%1
+   sq<de>b\t%0,%1"
   [(set_attr "op_type" "RRE,RXE")
-   (set_attr "type" "fsqrtdf")])
+   (set_attr "type" "fsqrt<mode>")])
 
-;
-; sqrtsf2 instruction pattern(s).
-;
-
-(define_insn "sqrtsf2"
-  [(set (match_operand:SF 0 "register_operand" "=f,f")
-       (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
-  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "@
-   sqebr\t%0,%1
-   sqeb\t%0,%1"
-  [(set_attr "op_type" "RRE,RXE")
-   (set_attr "type" "fsqrtsf")])
 
 ;;
 ;;- One complement instructions.
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