* arm.md (addsi3_carryin_shift): Add missing register constraints.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@74694 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d1cf3a4..6787173 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2003-12-16  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (addsi3_carryin_shift): Add missing register constraints.
+
 2003-12-16  Loren James Rittle  <ljrittle@acm.org>
 
        * testsuite/g++.old-deja/g++.eh/badalloc1.C: Tweak to

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 980bb22..d45b071 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -792,13 +792,13 @@
 )
 
 (define_insn "*addsi3_carryin_shift"
-  [(set (match_operand:SI 0 "s_register_operand" "")
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
        (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
                 (plus:SI
                   (match_operator:SI 2 "shift_operator"
-                     [(match_operand:SI 3 "s_register_operand" "")
-                      (match_operand:SI 4 "reg_or_int_operand" "")])
-                   (match_operand:SI 1 "s_register_operand" ""))))]
+                     [(match_operand:SI 3 "s_register_operand" "r")
+                      (match_operand:SI 4 "reg_or_int_operand" "rM")])
+                   (match_operand:SI 1 "s_register_operand" "r"))))]
   "TARGET_ARM"
   "adc%?\\t%0, %1, %3%S2"
   [(set_attr "conds" "use")]