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* arm.md (storehi): Avoid use of explicit subreg.
authorrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 12 Nov 2003 16:15:07 +0000 (16:15 +0000)
committerrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 12 Nov 2003 16:15:07 +0000 (16:15 +0000)
(storehi_bigend, storeinthi, movhi_bigend): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@73496 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/arm/arm.md

index 393e405..28c9c3c 100644 (file)
@@ -1,3 +1,8 @@
+2003-11-12  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (storehi): Avoid use of explicit subreg.
+       (storehi_bigend, storeinthi, movhi_bigend): Likewise.
+
 2003-11-12  J"orn Rennecke <joern.rennecke@superh.com>
 
        * config/sh/sh.md (prefetch): New pattern.
index 9a693a8..289687f 100644 (file)
    (set (match_dup 2)
        (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
    ;; store the high byte
-   (set (match_dup 4) (subreg:QI (match_dup 2) 0))]    ;explicit subreg safe
+   (set (match_dup 4) (match_dup 5))]
   "TARGET_ARM"
   "
   {
     operands[1] = adjust_address (operands[1], QImode, 0);
     operands[3] = gen_lowpart (QImode, operands[0]);
     operands[0] = gen_lowpart (SImode, operands[0]);
-    operands[2] = gen_reg_rtx (SImode); 
+    operands[2] = gen_reg_rtx (SImode);
+    operands[5] = gen_lowpart (QImode, operands[2]);
   }"
 )
 
   [(set (match_dup 4) (match_dup 3))
    (set (match_dup 2)
        (ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
-   (set (match_operand 1 "" "")        (subreg:QI (match_dup 2) 3))]
+   (set (match_operand 1 "" "")        (match_dup 5))]
   "TARGET_ARM"
   "
   {
     operands[3] = gen_lowpart (QImode, operands[0]);
     operands[0] = gen_lowpart (SImode, operands[0]);
     operands[2] = gen_reg_rtx (SImode);
+    operands[5] = gen_lowpart (QImode, operands[2]);
   }"
 )
 
 ;; Subroutine to store a half word integer constant into memory.
 (define_expand "storeinthi"
   [(set (match_operand 0 "" "")
-       (subreg:QI (match_operand 1 "" "") 0))
+       (match_operand 1 "" ""))
    (set (match_dup 3) (match_dup 2))]
   "TARGET_ARM"
   "
     operands[3] = adjust_address (op0, QImode, 1);
     operands[0] = adjust_address (operands[0], QImode, 0);
     operands[2] = gen_lowpart (QImode, operands[2]);
+    operands[1] = gen_lowpart (QImode, operands[1]);
   }"
 )
 
    (set (match_dup 3)
        (ashiftrt:SI (match_dup 2) (const_int 16)))
    (set (match_operand:HI 0 "s_register_operand" "")
-       (subreg:HI (match_dup 3) 0))]
+       (match_dup 4))]
   "TARGET_ARM"
   "
   operands[2] = gen_reg_rtx (SImode);
   operands[3] = gen_reg_rtx (SImode);
+  operands[4] = gen_lowpart (HImode, operands[3]);
   "
 )