[(set_attr "type" "vecsimple")])
(define_insn "altivec_dst"
- [(unspec [(match_operand:SI 0 "register_operand" "b")
+ [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 190)]
"TARGET_ALTIVEC"
- "dst %0,%1,%2"
+ "dst %P0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dstt"
- [(unspec [(match_operand:SI 0 "register_operand" "b")
+ [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 191)]
"TARGET_ALTIVEC"
- "dstt %0,%1,%2"
+ "dstt %P0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dstst"
- [(unspec [(match_operand:SI 0 "register_operand" "b")
+ [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 192)]
"TARGET_ALTIVEC"
- "dstst %0,%1,%2"
+ "dstst %P0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_dststt"
- [(unspec [(match_operand:SI 0 "register_operand" "b")
+ [(unspec [(match_operand:V4SI 0 "memory_operand" "Q")
(match_operand:SI 1 "register_operand" "r")
(match_operand:QI 2 "immediate_operand" "i")] 193)]
"TARGET_ALTIVEC"
- "dststt %0,%1,%2"
+ "dststt %P0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_lvsl"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r")] 194))]
+ (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 194))]
"TARGET_ALTIVEC"
- "lvsl %0,%1,%2"
+ "lvsl %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvsr"
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r")] 195))]
+ (unspec:V16QI [(match_operand 1 "memory_operand" "m")] 195))]
"TARGET_ALTIVEC"
- "lvsr %0,%1,%2"
+ "lvsr %0,%y1"
[(set_attr "type" "vecload")])
;; Parallel some of the LVE* and STV*'s with unspecs because some have
(define_insn "altivec_lvebx"
[(parallel
[(set (match_operand:V16QI 0 "register_operand" "=v")
- (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r"))))
+ (match_operand:V16QI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 196)])]
"TARGET_ALTIVEC"
- "lvebx %0,%1,%2"
+ "lvebx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvehx"
[(parallel
[(set (match_operand:V8HI 0 "register_operand" "=v")
- (mem:V8HI
- (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r"))
- (const_int -2))))
+ (match_operand:V8HI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 197)])]
"TARGET_ALTIVEC"
- "lvehx %0,%1,%2"
+ "lvehx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvewx"
[(parallel
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r"))
- (const_int -4))))
+ (match_operand:V4SI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 198)])]
"TARGET_ALTIVEC"
- "lvewx %0,%1,%2"
+ "lvewx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvxl"
[(parallel
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r"))))
+ (match_operand:V4SI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 213)])]
"TARGET_ALTIVEC"
- "lvxl %0,%1,%2"
+ "lvxl %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx"
[(set (match_operand:V4SI 0 "register_operand" "=v")
- (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "register_operand" "r"))))]
+ (match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
- "lvx %0,%1,%2"
+ "lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_stvx"
[(parallel
- [(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -16)))
- (match_operand:V4SI 2 "register_operand" "v"))
+ [(set (match_operand:V4SI 0 "memory_operand" "=m")
+ (match_operand:V4SI 1 "register_operand" "v"))
(unspec [(const_int 0)] 201)])]
"TARGET_ALTIVEC"
- "stvx %2,%0,%1"
+ "stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvxl"
[(parallel
- [(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -16)))
- (match_operand:V4SI 2 "register_operand" "v"))
+ [(set (match_operand:V4SI 0 "memory_operand" "=m")
+ (match_operand:V4SI 1 "register_operand" "v"))
(unspec [(const_int 0)] 202)])]
"TARGET_ALTIVEC"
- "stvxl %2,%0,%1"
+ "stvxl %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvebx"
[(parallel
- [(set (mem:V16QI
- (plus:SI (match_operand:SI 0 "register_operand" "b")
- (match_operand:SI 1 "register_operand" "r")))
- (match_operand:V16QI 2 "register_operand" "v"))
+ [(set (match_operand:V16QI 0 "memory_operand" "=m")
+ (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC"
- "stvebx %2,%0,%1"
+ "stvebx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvehx"
[(parallel
- [(set (mem:V8HI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -2)))
- (match_operand:V8HI 2 "register_operand" "v"))
+ [(set (match_operand:V8HI 0 "memory_operand" "=m")
+ (match_operand:V8HI 1 "register_operand" "v"))
(unspec [(const_int 0)] 204)])]
"TARGET_ALTIVEC"
- "stvehx %2,%0,%1"
+ "stvehx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvewx"
[(parallel
- [(set (mem:V4SI
- (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b")
- (match_operand:SI 1 "register_operand" "r"))
- (const_int -4)))
- (match_operand:V4SI 2 "register_operand" "v"))
+ [(set (match_operand:V4SI 0 "memory_operand" "=m")
+ (match_operand:V4SI 1 "register_operand" "v"))
(unspec [(const_int 0)] 205)])]
"TARGET_ALTIVEC"
- "stvewx %2,%0,%1"
+ "stvewx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "absv16qi2"
static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
static rtx altivec_expand_predicate_builtin (enum insn_code,
const char *, tree, rtx);
+static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
static rtx altivec_expand_stv_builtin (enum insn_code, tree);
static void rs6000_parse_abi_options (void);
static void rs6000_parse_alignment_option (void);
}
static rtx
+altivec_expand_lv_builtin (icode, arglist, target)
+ enum insn_code icode;
+ tree arglist;
+ rtx target;
+{
+ rtx pat, addr;
+ tree arg0 = TREE_VALUE (arglist);
+ tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
+ enum machine_mode mode0 = Pmode;
+ enum machine_mode mode1 = Pmode;
+ rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
+ rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
+
+ if (icode == CODE_FOR_nothing)
+ /* Builtin not supported on this processor. */
+ return 0;
+
+ /* If we got invalid arguments bail out before generating bad rtl. */
+ if (arg0 == error_mark_node || arg1 == error_mark_node)
+ return const0_rtx;
+
+ if (target == 0
+ || GET_MODE (target) != tmode
+ || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
+ target = gen_reg_rtx (tmode);
+
+ op1 = copy_to_mode_reg (mode1, op1);
+
+ if (op0 == const0_rtx)
+ {
+ addr = gen_rtx_MEM (tmode, op1);
+ }
+ else
+ {
+ op0 = copy_to_mode_reg (mode0, op0);
+ addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
+ }
+
+ pat = GEN_FCN (icode) (target, addr);
+
+ if (! pat)
+ return 0;
+ emit_insn (pat);
+
+ return target;
+}
+
+static rtx
altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
{
tree arg0 = TREE_VALUE (arglist);
rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
- rtx pat;
- enum machine_mode mode0 = insn_data[icode].operand[0].mode;
- enum machine_mode mode1 = insn_data[icode].operand[1].mode;
- enum machine_mode mode2 = insn_data[icode].operand[2].mode;
+ rtx pat, addr;
+ enum machine_mode tmode = insn_data[icode].operand[0].mode;
+ enum machine_mode mode1 = Pmode;
+ enum machine_mode mode2 = Pmode;
/* Invalid arguments. Bail before doing anything stoopid! */
if (arg0 == error_mark_node
|| arg2 == error_mark_node)
return const0_rtx;
- if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
- op0 = copy_to_mode_reg (mode2, op0);
- if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
- op1 = copy_to_mode_reg (mode0, op1);
- if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
- op2 = copy_to_mode_reg (mode1, op2);
+ if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
+ op0 = copy_to_mode_reg (tmode, op0);
+
+ op2 = copy_to_mode_reg (mode2, op2);
+
+ if (op1 == const0_rtx)
+ {
+ addr = gen_rtx_MEM (tmode, op2);
+ }
+ else
+ {
+ op1 = copy_to_mode_reg (mode1, op1);
+ addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
+ }
- pat = GEN_FCN (icode) (op1, op2, op0);
+ pat = GEN_FCN (icode) (addr, op0);
if (pat)
emit_insn (pat);
return NULL_RTX;
}
if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
- op0 = copy_to_mode_reg (mode0, op0);
+ op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
op1 = copy_to_mode_reg (mode1, op1);
switch (fcode)
{
case ALTIVEC_BUILTIN_LVSL:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsl,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
arglist, target);
case ALTIVEC_BUILTIN_LVSR:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsr,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
arglist, target);
case ALTIVEC_BUILTIN_LVEBX:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvebx,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
arglist, target);
case ALTIVEC_BUILTIN_LVEHX:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvehx,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
arglist, target);
case ALTIVEC_BUILTIN_LVEWX:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvewx,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
arglist, target);
case ALTIVEC_BUILTIN_LVXL:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvxl,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
arglist, target);
case ALTIVEC_BUILTIN_LVX:
- return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvx,
+ return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
arglist, target);
default:
break;
tree void_ftype_qi
= build_function_type_list (void_type_node, char_type_node, NULL_TREE);
- tree v16qi_ftype_int_pcvoid
+ tree v16qi_ftype_long_pcvoid
= build_function_type_list (V16QI_type_node,
- integer_type_node, pcvoid_type_node, NULL_TREE);
- tree v8hi_ftype_int_pcvoid
+ long_integer_type_node, pcvoid_type_node, NULL_TREE);
+ tree v8hi_ftype_long_pcvoid
= build_function_type_list (V8HI_type_node,
- integer_type_node, pcvoid_type_node, NULL_TREE);
- tree v4si_ftype_int_pcvoid
+ long_integer_type_node, pcvoid_type_node, NULL_TREE);
+ tree v4si_ftype_long_pcvoid
= build_function_type_list (V4SI_type_node,
- integer_type_node, pcvoid_type_node, NULL_TREE);
+ long_integer_type_node, pcvoid_type_node, NULL_TREE);
- tree void_ftype_v4si_int_pvoid
+ tree void_ftype_v4si_long_pvoid
= build_function_type_list (void_type_node,
- V4SI_type_node, integer_type_node,
+ V4SI_type_node, long_integer_type_node,
pvoid_type_node, NULL_TREE);
- tree void_ftype_v16qi_int_pvoid
+ tree void_ftype_v16qi_long_pvoid
= build_function_type_list (void_type_node,
- V16QI_type_node, integer_type_node,
+ V16QI_type_node, long_integer_type_node,
pvoid_type_node, NULL_TREE);
- tree void_ftype_v8hi_int_pvoid
+ tree void_ftype_v8hi_long_pvoid
= build_function_type_list (void_type_node,
- V8HI_type_node, integer_type_node,
+ V8HI_type_node, long_integer_type_node,
pvoid_type_node, NULL_TREE);
tree int_ftype_int_v8hi_v8hi
= build_function_type_list (integer_type_node,
def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSL);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSR);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEBX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEHX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEWX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVXL);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX);
- def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
+ def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
/* Add the DST variants. */
d = (struct builtin_description *) bdesc_dst;
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