2007-03-19 Andreas Krebbel <krebbel1@de.ibm.com>

	* config/s390/s390.md: Only non-functional changes.  Renamed
	FPR mode macro to BFP all over the file.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@123057 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f2671f0..d4f136e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
 2007-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>
 
+       * config/s390/s390.md: Only non-functional changes.  Renamed
+       FPR mode macro to BFP all over the file.
+
+2007-03-19  Andreas Krebbel  <krebbel1@de.ibm.com>
+
        * config/s390/s390.md (UNSPEC_COPYSIGN): New constant.
        (op_type attribute): RRF instruction type added.
        (fT0): New mode attribute.

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index fbb2f9a..27733a0 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -214,7 +214,7 @@
 
 ;; This mode macro allows floating point patterns to be generated from the
 ;; same template.
-(define_mode_macro FPR [TF DF SF])
+(define_mode_macro BFP [TF DF SF])
 (define_mode_macro DSF [DF SF])
 
 ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated
@@ -256,20 +256,20 @@
                          (plus "add") (minus "sub") (mult "nand")])
 
 
-;; In FPR templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
+;; In BFP templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode,
 ;; "ltdbr" in DFmode, and "ltebr" in SFmode.
 (define_mode_attr xde [(TF "x") (DF "d") (SF "e")])
 
-;; In FPR templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
+;; In BFP templates, a string like "m<dee>br" will expand to "mxbr" in TFmode,
 ;; "mdbr" in DFmode, and "meebr" in SFmode.
 (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")])
 
-;; In FPR templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
+;; In BFP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise.
 ;; Likewise for "<RXe>".
 (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")])
 (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")])
 
-;; In FPR templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
+;; In BFP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
 ;; This is used to disable the memory alternative in TFmode patterns.
 (define_mode_attr Rf [(TF "f") (DF "R") (SF "R")])
 
@@ -362,8 +362,8 @@
 
 (define_expand "cmp<mode>"
   [(set (reg:CC CC_REGNUM)
-        (compare:CC (match_operand:FPR 0 "register_operand" "")
-                    (match_operand:FPR 1 "general_operand" "")))]
+        (compare:CC (match_operand:BFP 0 "register_operand" "")
+                    (match_operand:BFP 1 "general_operand" "")))]
   "TARGET_HARD_FLOAT"
 {
   s390_compare_op0 = operands[0];
@@ -753,8 +753,8 @@
 ; ltxbr, ltdbr, ltebr
 (define_insn "*cmp<mode>_ccs_0"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:FPR 0 "register_operand" "f")
-                 (match_operand:FPR 1 "const0_operand" "")))]
+        (compare (match_operand:BFP 0 "register_operand" "f")
+                 (match_operand:BFP 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lt<xde>br\t%0,%0"
    [(set_attr "op_type" "RRE")
@@ -763,8 +763,8 @@
 ; ltxr, ltdr, lter
 (define_insn "*cmp<mode>_ccs_0_ibm"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:FPR 0 "register_operand" "f")
-                 (match_operand:FPR 1 "const0_operand" "")))]
+        (compare (match_operand:BFP 0 "register_operand" "f")
+                 (match_operand:BFP 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "lt<xde>r\t%0,%0"
    [(set_attr "op_type" "<RRe>")
@@ -773,8 +773,8 @@
 ; cxbr, cdbr, cebr, cxb, cdb, ceb
 (define_insn "*cmp<mode>_ccs"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:FPR 0 "register_operand" "f,f")
-                 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
+        (compare (match_operand:BFP 0 "register_operand" "f,f")
+                 (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    c<xde>br\t%0,%1
@@ -785,8 +785,8 @@
 ; cxr, cdr, cer, cx, cd, ce
 (define_insn "*cmp<mode>_ccs_ibm"
   [(set (reg CC_REGNUM)
-        (compare (match_operand:FPR 0 "register_operand" "f,f")
-                 (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
+        (compare (match_operand:BFP 0 "register_operand" "f,f")
+                 (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
    c<xde>r\t%0,%1
@@ -1554,7 +1554,7 @@
   operands[1] = replace_equiv_address (operands[1], addr);
 })
 
-; TFmode in FPRs splitters
+; TFmode in BFPs splitters
 
 (define_split
   [(set (match_operand:TF 0 "register_operand" "")
@@ -3148,31 +3148,31 @@
 ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s).
 ;
 
-(define_expand "fixuns_trunc<FPR:mode><GPR:mode>2"
+(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
   [(set (match_operand:GPR 0 "register_operand" "")
-        (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))]
+        (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
-  rtx temp = gen_reg_rtx (<FPR:MODE>mode);
+  rtx temp = gen_reg_rtx (<BFP:MODE>mode);
   REAL_VALUE_TYPE cmp, sub;
   
-  operands[1] = force_reg (<FPR:MODE>mode, operands[1]);
+  operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
   real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1);
   real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode));
   
-  emit_insn (gen_cmp<FPR:mode> (operands[1],
-       CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode)));
+  emit_insn (gen_cmp<BFP:mode> (operands[1],
+       CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode)));
   emit_jump_insn (gen_blt (label1));
-  emit_insn (gen_sub<FPR:mode>3 (temp, operands[1],
-       CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode)));
-  emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp,
+  emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
+       CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
+  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0], temp,
        GEN_INT(7)));
   emit_jump (label2);
 
   emit_label (label1);
-  emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0],
+  emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_ieee (operands[0],
        operands[1], GEN_INT(5)));
   emit_label (label2);
   DONE;
@@ -3190,13 +3190,13 @@
 })
 
 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
-(define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee"
+(define_insn "fix_trunc<BFP:mode><GPR:mode>2_ieee"
   [(set (match_operand:GPR 0 "register_operand" "=d")
-        (fix:GPR (match_operand:FPR 1 "register_operand" "f")))
+        (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
    (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "c<GPR:gf><FPR:xde>br\t%0,%h2,%1"
+  "c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "ftoi")])
 
@@ -3290,8 +3290,8 @@
 
 ; cxgbr, cdgbr, cegbr
 (define_insn "floatdi<mode>2"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (float:FPR (match_operand:DI 1 "register_operand" "d")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (float:BFP (match_operand:DI 1 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "c<xde>gbr\t%0,%1"
   [(set_attr "op_type" "RRE")
@@ -3299,8 +3299,8 @@
 
 ; cxfbr, cdfbr, cefbr
 (define_insn "floatsi<mode>2_ieee"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (float:FPR (match_operand:SI 1 "register_operand" "d")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (float:BFP (match_operand:SI 1 "register_operand" "d")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "c<xde>fbr\t%0,%1"
   [(set_attr "op_type" "RRE")
@@ -3883,18 +3883,18 @@
 
 (define_expand "add<mode>3"
   [(parallel
-    [(set (match_operand:FPR 0 "register_operand" "=f,f")
-          (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                    (match_operand:FPR 2 "general_operand" "f,<Rf>")))
+    [(set (match_operand:BFP 0 "register_operand" "=f,f")
+          (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                    (match_operand:BFP 2 "general_operand" "f,<Rf>")))
      (clobber (reg:CC CC_REGNUM))])]
   "TARGET_HARD_FLOAT"
   "")
 
 ; axbr, adbr, aebr, axb, adb, aeb
 (define_insn "*add<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:FPR 2 "general_operand" "f,<Rf>")))
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
@@ -3906,11 +3906,11 @@
 ; axbr, adbr, aebr, axb, adb, aeb
 (define_insn "*add<mode>3_cc"
   [(set (reg CC_REGNUM)
-       (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                          (match_operand:FPR 2 "general_operand" "f,<Rf>"))
-                (match_operand:FPR 3 "const0_operand" "")))
-   (set (match_operand:FPR 0 "register_operand" "=f,f")
-       (plus:FPR (match_dup 1) (match_dup 2)))]
+       (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                          (match_operand:BFP 2 "general_operand" "f,<Rf>"))
+                (match_operand:BFP 3 "const0_operand" "")))
+   (set (match_operand:BFP 0 "register_operand" "=f,f")
+       (plus:BFP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    a<xde>br\t%0,%2
@@ -3921,10 +3921,10 @@
 ; axbr, adbr, aebr, axb, adb, aeb
 (define_insn "*add<mode>3_cconly"
   [(set (reg CC_REGNUM)
-       (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                          (match_operand:FPR 2 "general_operand" "f,<Rf>"))
-                (match_operand:FPR 3 "const0_operand" "")))
-   (clobber (match_scratch:FPR 0 "=f,f"))]
+       (compare (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                          (match_operand:BFP 2 "general_operand" "f,<Rf>"))
+                (match_operand:BFP 3 "const0_operand" "")))
+   (clobber (match_scratch:BFP 0 "=f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    a<xde>br\t%0,%2
@@ -3934,9 +3934,9 @@
 
 ; axr, adr, aer, ax, ad, ae
 (define_insn "*add<mode>3_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:FPR 2 "general_operand" "f,<Rf>")))
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (plus:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
@@ -4226,18 +4226,18 @@
 
 (define_expand "sub<mode>3"
   [(parallel
-    [(set (match_operand:FPR 0 "register_operand" "=f,f")
-          (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                     (match_operand:FPR 2 "general_operand" "f,R")))
+    [(set (match_operand:BFP 0 "register_operand" "=f,f")
+          (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                     (match_operand:BFP 2 "general_operand" "f,R")))
      (clobber (reg:CC CC_REGNUM))])]
   "TARGET_HARD_FLOAT"
   "")
 
 ; sxbr, sdbr, sebr, sxb, sdb, seb
 (define_insn "*sub<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                   (match_operand:FPR 2 "general_operand" "f,<Rf>")))
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                   (match_operand:BFP 2 "general_operand" "f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
@@ -4249,11 +4249,11 @@
 ; sxbr, sdbr, sebr, sxb, sdb, seb
 (define_insn "*sub<mode>3_cc"
   [(set (reg CC_REGNUM)
-       (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
-                           (match_operand:FPR 2 "general_operand" "f,<Rf>"))
-                (match_operand:FPR 3 "const0_operand" "")))
-   (set (match_operand:FPR 0 "register_operand" "=f,f")
-       (minus:FPR (match_dup 1) (match_dup 2)))]
+       (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
+                           (match_operand:BFP 2 "general_operand" "f,<Rf>"))
+                (match_operand:BFP 3 "const0_operand" "")))
+   (set (match_operand:BFP 0 "register_operand" "=f,f")
+       (minus:BFP (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    s<xde>br\t%0,%2
@@ -4264,10 +4264,10 @@
 ; sxbr, sdbr, sebr, sxb, sdb, seb
 (define_insn "*sub<mode>3_cconly"
   [(set (reg CC_REGNUM)
-       (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0")
-                           (match_operand:FPR 2 "general_operand" "f,<Rf>"))
-                (match_operand:FPR 3 "const0_operand" "")))
-   (clobber (match_scratch:FPR 0 "=f,f"))]
+       (compare (minus:BFP (match_operand:BFP 1 "nonimmediate_operand" "0,0")
+                           (match_operand:BFP 2 "general_operand" "f,<Rf>"))
+                (match_operand:BFP 3 "const0_operand" "")))
+   (clobber (match_scratch:BFP 0 "=f,f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    s<xde>br\t%0,%2
@@ -4277,9 +4277,9 @@
 
 ; sxr, sdr, ser, sx, sd, se
 (define_insn "*sub<mode>3_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (minus:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                   (match_operand:FPR 2 "general_operand" "f,<Rf>")))
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (minus:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                   (match_operand:BFP 2 "general_operand" "f,<Rf>")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
@@ -4535,17 +4535,17 @@
 ;
 
 (define_expand "mul<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT"
   "")
 
 ; mxbr mdbr, meebr, mxb, mxb, meeb
 (define_insn "*mul<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    m<xdee>br\t%0,%2
@@ -4555,9 +4555,9 @@
 
 ; mxr, mdr, mer, mx, md, me
 (define_insn "*mul<mode>3_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0")
-                  (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (mult:BFP (match_operand:BFP 1 "nonimmediate_operand" "%0,0")
+                  (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
    m<xde>r\t%0,%2
@@ -5014,17 +5014,17 @@
 ;
 
 (define_expand "div<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT"
   "")
 
 ; dxbr, ddbr, debr, dxb, ddb, deb
 (define_insn "*div<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    d<xde>br\t%0,%2
@@ -5034,9 +5034,9 @@
 
 ; dxr, ddr, der, dx, dd, de
 (define_insn "*div<mode>3_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-        (div:FPR (match_operand:FPR 1 "register_operand" "0,0")
-                 (match_operand:FPR 2 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+        (div:BFP (match_operand:BFP 1 "register_operand" "0,0")
+                 (match_operand:BFP 2 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
    d<xde>r\t%0,%2
@@ -6014,8 +6014,8 @@
 
 (define_expand "neg<mode>2"
   [(parallel
-    [(set (match_operand:FPR 0 "register_operand" "=f")
-          (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+    [(set (match_operand:BFP 0 "register_operand" "=f")
+          (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
      (clobber (reg:CC CC_REGNUM))])]
   "TARGET_HARD_FLOAT"
   "")
@@ -6023,10 +6023,10 @@
 ; lcxbr, lcdbr, lcebr
 (define_insn "*neg<mode>2_cc"
   [(set (reg CC_REGNUM)
-        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (set (match_operand:FPR 0 "register_operand" "=f")
-        (neg:FPR (match_dup 1)))]
+        (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (set (match_operand:BFP 0 "register_operand" "=f")
+        (neg:BFP (match_dup 1)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lc<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6035,9 +6035,9 @@
 ; lcxbr, lcdbr, lcebr
 (define_insn "*neg<mode>2_cconly"
   [(set (reg CC_REGNUM)
-        (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f"))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (clobber (match_scratch:FPR 0 "=f"))]
+        (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f"))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (clobber (match_scratch:BFP 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lc<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6045,8 +6045,8 @@
 
 ; lcdfr
 (define_insn "*neg<mode>2_nocc"
-  [(set (match_operand:FPR 0 "register_operand"          "=f")
-        (neg:FPR (match_operand:FPR 1 "register_operand" "<fT0>")))]
+  [(set (match_operand:BFP 0 "register_operand"          "=f")
+        (neg:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
   "TARGET_HARD_FLOAT && TARGET_DFP"
   "lcdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6054,8 +6054,8 @@
 
 ; lcxbr, lcdbr, lcebr
 (define_insn "*neg<mode>2"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lc<xde>br\t%0,%1"
@@ -6064,8 +6064,8 @@
 
 ; lcxr, lcdr, lcer
 (define_insn "*neg<mode>2_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (neg:FPR (match_operand:FPR 1 "register_operand" "f")))
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "lc<xde>r\t%0,%1"
@@ -6137,8 +6137,8 @@
 
 (define_expand "abs<mode>2"
   [(parallel
-    [(set (match_operand:FPR 0 "register_operand" "=f")
-          (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+    [(set (match_operand:BFP 0 "register_operand" "=f")
+          (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
      (clobber (reg:CC CC_REGNUM))])]
   "TARGET_HARD_FLOAT"
   "")
@@ -6146,10 +6146,10 @@
 ; lpxbr, lpdbr, lpebr
 (define_insn "*abs<mode>2_cc"
   [(set (reg CC_REGNUM)
-        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (set (match_operand:FPR 0 "register_operand" "=f")
-        (abs:FPR (match_dup 1)))]
+        (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (set (match_operand:BFP 0 "register_operand" "=f")
+        (abs:BFP (match_dup 1)))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lp<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6158,9 +6158,9 @@
 ; lpxbr, lpdbr, lpebr
 (define_insn "*abs<mode>2_cconly"
   [(set (reg CC_REGNUM)
-        (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f"))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (clobber (match_scratch:FPR 0 "=f"))]
+        (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f"))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (clobber (match_scratch:BFP 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lp<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6168,8 +6168,8 @@
 
 ; lpdfr
 (define_insn "*abs<mode>2_nocc"
-  [(set (match_operand:FPR 0 "register_operand"          "=f")
-        (abs:FPR (match_operand:FPR 1 "register_operand" "<fT0>")))]
+  [(set (match_operand:BFP 0 "register_operand"          "=f")
+        (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>")))]
   "TARGET_HARD_FLOAT && TARGET_DFP"
   "lpdfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6177,8 +6177,8 @@
 
 ; lpxbr, lpdbr, lpebr
 (define_insn "*abs<mode>2"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "lp<xde>br\t%0,%1"
@@ -6187,8 +6187,8 @@
 
 ; lpxr, lpdr, lper
 (define_insn "*abs<mode>2_ibm"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "lp<xde>r\t%0,%1"
@@ -6261,10 +6261,10 @@
 ; lnxbr, lndbr, lnebr
 (define_insn "*negabs<mode>2_cc"
   [(set (reg CC_REGNUM)
-        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (set (match_operand:FPR 0 "register_operand" "=f")
-        (neg:FPR (abs:FPR (match_dup 1))))]
+        (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (set (match_operand:BFP 0 "register_operand" "=f")
+        (neg:BFP (abs:BFP (match_dup 1))))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "ln<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6273,9 +6273,9 @@
 ; lnxbr, lndbr, lnebr
 (define_insn "*negabs<mode>2_cconly"
   [(set (reg CC_REGNUM)
-        (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))
-                 (match_operand:FPR 2 "const0_operand" "")))
-   (clobber (match_scratch:FPR 0 "=f"))]
+        (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
+                 (match_operand:BFP 2 "const0_operand" "")))
+   (clobber (match_scratch:BFP 0 "=f"))]
   "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "ln<xde>br\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6283,8 +6283,8 @@
 
 ; lndfr
 (define_insn "*negabs<mode>2_nocc"
-  [(set (match_operand:FPR 0 "register_operand"                   "=f")
-        (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "<fT0>"))))]
+  [(set (match_operand:BFP 0 "register_operand"                   "=f")
+        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "<fT0>"))))]
   "TARGET_HARD_FLOAT && TARGET_DFP"
   "lndfr\t%0,%1"
   [(set_attr "op_type"  "RRE")
@@ -6292,8 +6292,8 @@
 
 ; lnxbr, lndbr, lnebr
 (define_insn "*negabs<mode>2"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-        (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))))
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+        (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "ln<xde>br\t%0,%1"
@@ -6306,9 +6306,9 @@
 
 ; cpsdr
 (define_insn "copysign<mode>3"
-  [(set (match_operand:FPR 0 "register_operand" "=f")
-       (unspec:FPR [(match_operand:FPR 1 "register_operand" "<fT0>")
-                    (match_operand:FPR 2 "register_operand" "f")] 
+  [(set (match_operand:BFP 0 "register_operand" "=f")
+       (unspec:BFP [(match_operand:BFP 1 "register_operand" "<fT0>")
+                    (match_operand:BFP 2 "register_operand" "f")] 
                    UNSPEC_COPYSIGN))]
   "TARGET_HARD_FLOAT && TARGET_DFP"
   "cpsdr\t%0,%2,%1"
@@ -6325,8 +6325,8 @@
 
 ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb
 (define_insn "sqrt<mode>2"
-  [(set (match_operand:FPR 0 "register_operand" "=f,f")
-       (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))]
+  [(set (match_operand:BFP 0 "register_operand" "=f,f")
+       (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
    sq<xde>br\t%0,%1