;; Extension insns.
;; Those for integer source operand are ordered widest source type first.
-(define_expand "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "
-{
- if (optimize && GET_CODE (operands[1]) == MEM)
- operands[1] = force_not_mem (operands[1]);
-
- if (GET_CODE (operands[1]) != MEM)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx temp = gen_reg_rtx (DImode);
- rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
+;; In 64 bit mode, 32 bit values in general registers are always
+;; correctly sign extended. That means that if the target is a
+;; general register, we can sign extend from SImode to DImode just by
+;; doing a move.
- emit_insn (gen_ashldi3 (temp, op1, shift));
- emit_insn (gen_ashrdi3 (operands[0], temp, shift));
- DONE;
- }
-}")
-
-(define_insn "extendsidi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
+(define_insn "extendsidi2"
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
"TARGET_64BIT"
"* return mips_move_1word (operands, insn, FALSE);"
- [(set_attr "type" "load")
+ [(set_attr "type" "move,load,load")
(set_attr "mode" "DI")
- (set_attr "length" "1,2")])
+ (set_attr "length" "1,1,2")])
;; These patterns originally accepted general_operands, however, slightly
;; better code is generated by only accepting register_operands, and then