options correctly. */
const struct mips_cpu_info mips_cpu_info_table[] = {
/* Entries for generic ISAs */
- { "mips1", PROCESSOR_R3000, 1 },
- { "mips2", PROCESSOR_R6000, 2 },
- { "mips3", PROCESSOR_R4000, 3 },
- { "mips4", PROCESSOR_R8000, 4 },
- { "mips32", PROCESSOR_4KC, 32 },
- { "mips32r2", PROCESSOR_M4K, 33 },
- { "mips64", PROCESSOR_5KC, 64 },
+ { "mips1", PROCESSOR_R3000, 1, 0 },
+ { "mips2", PROCESSOR_R6000, 2, 0 },
+ { "mips3", PROCESSOR_R4000, 3, 0 },
+ { "mips4", PROCESSOR_R8000, 4, 0 },
+ /* Prefer not to use branch-likely instructions for generic MIPS32rX
+ and MIPS64rX code. The instructions were officially deprecated
+ in revisions 2 and earlier, but revision 3 is likely to downgrade
+ that to a recommendation to avoid the instructions in code that
+ isn't tuned to a specific processor. */
+ { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
+ { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
+ { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
/* MIPS I */
- { "r3000", PROCESSOR_R3000, 1 },
- { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
- { "r3900", PROCESSOR_R3900, 1 },
+ { "r3000", PROCESSOR_R3000, 1, 0 },
+ { "r2000", PROCESSOR_R3000, 1, 0 }, /* = r3000 */
+ { "r3900", PROCESSOR_R3900, 1, 0 },
/* MIPS II */
- { "r6000", PROCESSOR_R6000, 2 },
+ { "r6000", PROCESSOR_R6000, 2, 0 },
/* MIPS III */
- { "r4000", PROCESSOR_R4000, 3 },
- { "vr4100", PROCESSOR_R4100, 3 },
- { "vr4111", PROCESSOR_R4111, 3 },
- { "vr4120", PROCESSOR_R4120, 3 },
- { "vr4130", PROCESSOR_R4130, 3 },
- { "vr4300", PROCESSOR_R4300, 3 },
- { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
- { "r4600", PROCESSOR_R4600, 3 },
- { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
- { "r4650", PROCESSOR_R4650, 3 },
+ { "r4000", PROCESSOR_R4000, 3, 0 },
+ { "vr4100", PROCESSOR_R4100, 3, 0 },
+ { "vr4111", PROCESSOR_R4111, 3, 0 },
+ { "vr4120", PROCESSOR_R4120, 3, 0 },
+ { "vr4130", PROCESSOR_R4130, 3, 0 },
+ { "vr4300", PROCESSOR_R4300, 3, 0 },
+ { "r4400", PROCESSOR_R4000, 3, 0 }, /* = r4000 */
+ { "r4600", PROCESSOR_R4600, 3, 0 },
+ { "orion", PROCESSOR_R4600, 3, 0 }, /* = r4600 */
+ { "r4650", PROCESSOR_R4650, 3, 0 },
/* MIPS IV */
- { "r8000", PROCESSOR_R8000, 4 },
- { "vr5000", PROCESSOR_R5000, 4 },
- { "vr5400", PROCESSOR_R5400, 4 },
- { "vr5500", PROCESSOR_R5500, 4 },
- { "rm7000", PROCESSOR_R7000, 4 },
- { "rm9000", PROCESSOR_R9000, 4 },
+ { "r8000", PROCESSOR_R8000, 4, 0 },
+ { "vr5000", PROCESSOR_R5000, 4, 0 },
+ { "vr5400", PROCESSOR_R5400, 4, 0 },
+ { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
+ { "rm7000", PROCESSOR_R7000, 4, 0 },
+ { "rm9000", PROCESSOR_R9000, 4, 0 },
/* MIPS32 */
- { "4kc", PROCESSOR_4KC, 32 },
- { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
- { "4kp", PROCESSOR_4KP, 32 },
- { "4ksc", PROCESSOR_4KC, 32 },
+ { "4kc", PROCESSOR_4KC, 32, 0 },
+ { "4km", PROCESSOR_4KC, 32, 0 }, /* = 4kc */
+ { "4kp", PROCESSOR_4KP, 32, 0 },
+ { "4ksc", PROCESSOR_4KC, 32, 0 },
/* MIPS32 Release 2 */
- { "m4k", PROCESSOR_M4K, 33 },
- { "4kec", PROCESSOR_4KC, 33 },
- { "4kem", PROCESSOR_4KC, 33 },
- { "4kep", PROCESSOR_4KP, 33 },
- { "4ksd", PROCESSOR_4KC, 33 },
-
- { "24kc", PROCESSOR_24KC, 33 },
- { "24kf2_1", PROCESSOR_24KF2_1, 33 },
- { "24kf", PROCESSOR_24KF2_1, 33 },
- { "24kf1_1", PROCESSOR_24KF1_1, 33 },
- { "24kfx", PROCESSOR_24KF1_1, 33 },
- { "24kx", PROCESSOR_24KF1_1, 33 },
-
- { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
- { "24kef2_1", PROCESSOR_24KF2_1, 33 },
- { "24kef", PROCESSOR_24KF2_1, 33 },
- { "24kef1_1", PROCESSOR_24KF1_1, 33 },
- { "24kefx", PROCESSOR_24KF1_1, 33 },
- { "24kex", PROCESSOR_24KF1_1, 33 },
-
- { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
- { "34kf2_1", PROCESSOR_24KF2_1, 33 },
- { "34kf", PROCESSOR_24KF2_1, 33 },
- { "34kf1_1", PROCESSOR_24KF1_1, 33 },
- { "34kfx", PROCESSOR_24KF1_1, 33 },
- { "34kx", PROCESSOR_24KF1_1, 33 },
-
- { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
- { "74kf2_1", PROCESSOR_74KF2_1, 33 },
- { "74kf", PROCESSOR_74KF2_1, 33 },
- { "74kf1_1", PROCESSOR_74KF1_1, 33 },
- { "74kfx", PROCESSOR_74KF1_1, 33 },
- { "74kx", PROCESSOR_74KF1_1, 33 },
- { "74kf3_2", PROCESSOR_74KF3_2, 33 },
+ { "m4k", PROCESSOR_M4K, 33, 0 },
+ { "4kec", PROCESSOR_4KC, 33, 0 },
+ { "4kem", PROCESSOR_4KC, 33, 0 },
+ { "4kep", PROCESSOR_4KP, 33, 0 },
+ { "4ksd", PROCESSOR_4KC, 33, 0 },
+
+ { "24kc", PROCESSOR_24KC, 33, 0 },
+ { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kf", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kx", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP */
+ { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kef", PROCESSOR_24KF2_1, 33, 0 },
+ { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
+ { "24kex", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP */
+ { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
+ { "34kf", PROCESSOR_24KF2_1, 33, 0 },
+ { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
+ { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
+ { "34kx", PROCESSOR_24KF1_1, 33, 0 },
+
+ { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2 */
+ { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
+ { "74kf", PROCESSOR_74KF2_1, 33, 0 },
+ { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kx", PROCESSOR_74KF1_1, 33, 0 },
+ { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
/* MIPS64 */
- { "5kc", PROCESSOR_5KC, 64 },
- { "5kf", PROCESSOR_5KF, 64 },
- { "20kc", PROCESSOR_20KC, 64 },
- { "sb1", PROCESSOR_SB1, 64 },
- { "sb1a", PROCESSOR_SB1A, 64 },
- { "sr71000", PROCESSOR_SR71000, 64 },
-
- /* End marker */
- { 0, 0, 0 }
+ { "5kc", PROCESSOR_5KC, 64, 0 },
+ { "5kf", PROCESSOR_5KF, 64, 0 },
+ { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
+ { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
};
/* Default costs. If these are used for a processor we should look
{
/* If neither -mbranch-likely nor -mno-branch-likely was given
on the command line, set MASK_BRANCHLIKELY based on the target
- architecture.
-
- By default, we enable use of Branch Likely instructions on
- all architectures which support them with the following
- exceptions: when creating MIPS32 or MIPS64 code, and when
- tuning for architectures where their use tends to hurt
- performance.
-
- The MIPS32 and MIPS64 architecture specifications say "Software
- is strongly encouraged to avoid use of Branch Likely
- instructions, as they will be removed from a future revision
- of the [MIPS32 and MIPS64] architecture." Therefore, we do not
- issue those instructions unless instructed to do so by
- -mbranch-likely. */
+ architecture and tuning flags. Annulled delay slots are a
+ size win, so we only consider the process-specific tuning
+ for !optimize_size. */
if (ISA_HAS_BRANCHLIKELY
- && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
- && !(TUNE_MIPS5500 || TUNE_SB1))
+ && (optimize_size
+ || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
target_flags |= MASK_BRANCHLIKELY;
else
target_flags &= ~MASK_BRANCHLIKELY;
}
- if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
- warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
+ else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
+ warning (0, "the %qs architecture does not support branch-likely"
+ " instructions", mips_arch_info->name);
/* The effect of -mabicalls isn't defined for the EABI. */
if (mips_abi == ABI_EABI && TARGET_ABICALLS)
static const struct mips_cpu_info *
mips_parse_cpu (const char *cpu_string)
{
- const struct mips_cpu_info *p;
+ unsigned int i;
const char *s;
/* In the past, we allowed upper-case CPU names, but it doesn't
if (strcasecmp (cpu_string, "default") == 0)
return 0;
- for (p = mips_cpu_info_table; p->name != 0; p++)
- if (mips_matching_cpu_name_p (p->name, cpu_string))
- return p;
+ for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
+ if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
+ return mips_cpu_info_table + i;
return 0;
}
static const struct mips_cpu_info *
mips_cpu_info_from_isa (int isa)
{
- const struct mips_cpu_info *p;
+ unsigned int i;
- for (p = mips_cpu_info_table; p->name != 0; p++)
- if (p->isa == isa)
- return p;
+ for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
+ if (mips_cpu_info_table[i].isa == isa)
+ return mips_cpu_info_table + i;
return 0;
}
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