prototype.
* config/arm/arm.c (arm_gen_return_addr_mask): New function.
* config/arm/arm.h (MASK_RETURN_ADDR): Use arm_gen_return_addr_mask
if not APCS26 and not Thumb or ARMv4-or-higher. Use gen_int_mode
rather than GEN_INT.
* config/arm/arm.md (UNSPEC_CHECK_ARCH): Define.
(return_addr_mask, *check_arch2): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@56883
138bc75d-0d04-0410-961f-
82ee72b054a4
+2002-09-06 Jason Thorpe <thorpej@wasabisystems.com>
+
+ * config/arm/arm-protos.h (arm_gen_return_addr_mask): New
+ prototype.
+ * config/arm/arm.c (arm_gen_return_addr_mask): New function.
+ * config/arm/arm.h (MASK_RETURN_ADDR): Use arm_gen_return_addr_mask
+ if not APCS26 and not Thumb or ARMv4-or-higher. Use gen_int_mode
+ rather than GEN_INT.
+ * config/arm/arm.md (UNSPEC_CHECK_ARCH): Define.
+ (return_addr_mask, *check_arch2): New.
+
2002-09-06 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.md ("*adddi3_cc", "*adddi3_cconly",
extern rtx arm_gen_rotated_half_load PARAMS ((rtx));
extern enum machine_mode arm_select_cc_mode PARAMS ((RTX_CODE, rtx, rtx));
extern rtx arm_gen_compare_reg PARAMS ((RTX_CODE, rtx, rtx));
+extern rtx arm_gen_return_addr_mask PARAMS ((void));
extern void arm_reload_in_hi PARAMS ((rtx *));
extern void arm_reload_out_hi PARAMS ((rtx *));
extern void arm_reorg PARAMS ((rtx));
return cc_reg;
}
+/* Generate a sequence of insns that will generate the correct return
+ address mask depending on the physical architecture that the program
+ is running on. */
+
+rtx
+arm_gen_return_addr_mask ()
+{
+ rtx reg = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_return_addr_mask (reg));
+ return reg;
+}
+
void
arm_reload_in_hi (operands)
rtx * operands;
in 26 bit mode, the condition codes must be masked out of the \
return address. This does not apply to ARM6 and later processors \
when running in 32 bit mode. */ \
- ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
- : (GEN_INT ((unsigned long)0xffffffff)))
+ ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \
+ : (arm_arch4 || TARGET_THUMB) ? \
+ (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
+ : arm_gen_return_addr_mask ())
\f
/* Define the codes that are matched by predicates in arm.c */
; instructions setting registers for EH handling
; and stack frame generation. Operand 0 is the
; register to "use".
+ (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
]
)
(set_attr "type" "load")]
)
+;; Generate a sequence of instructions to determine if the processor is
+;; in 26-bit or 32-bit mode, and return the appropriate return address
+;; mask.
+
+(define_expand "return_addr_mask"
+ [(set (match_dup 1)
+ (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ (const_int 0)))
+ (set (match_operand:SI 0 "s_register_operand" "")
+ (if_then_else:SI (eq (match_dup 1) (const_int 0))
+ (const_int -1)
+ (const_int 67108860)))] ; 0x03fffffc
+ "TARGET_ARM"
+ "
+ operands[1] = gen_rtx_REG (CC_NOOVmode, 24);
+ ")
+
+(define_insn "*check_arch2"
+ [(set (match_operand:CC_NOOV 0 "cc_register" "")
+ (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ (const_int 0)))]
+ "TARGET_ARM"
+ "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
+ [(set_attr "length" "8")
+ (set_attr "conds" "set")]
+)
+
;; Call subroutine returning any type.
(define_expand "untyped_call"