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(umulsidi3): Use uns_arith_operand not arith_operand.
authorwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 6 Oct 1993 04:08:07 +0000 (04:08 +0000)
committerwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 6 Oct 1993 04:08:07 +0000 (04:08 +0000)
(const_umulsidi3): Use uns_small_int not small_int.
(ashlsi3+1, ashlsi3+2): New patterns to replace shift
and compare with addcc.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@5628 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/config/sparc/sparc.md

index dcb96e9..684a435 100644 (file)
 (define_expand "umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
-                (zero_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
+                (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
   "TARGET_V8 || TARGET_SPARCLITE"
   "
 {
 (define_insn "const_umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
-                (match_operand:SI 2 "small_int" "I")))]
+                (match_operand:SI 2 "uns_small_int" "")))]
   "TARGET_V8 || TARGET_SPARCLITE"
   "umul %1,%2,%R0\;rd %%y,%0"
   [(set_attr "length" "2")])
   ""
   "sll %1,%2,%0")
 
+(define_insn ""
+  [(set (reg:CC_NOOV 0)
+       (compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
+                                   (const_int 1))
+                        (const_int 0)))]
+  ""
+  "addcc %0,%0,%%g0"
+  [(set_attr "type" "compare")])
+
+(define_insn ""
+  [(set (reg:CC_NOOV 0)
+       (compare:CC_NOOV (ashift:SI (match_operand:SI 1 "register_operand" "r")
+                                   (const_int 1))
+                        (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+       (ashift:SI (match_dup 1) (const_int 1)))]
+  ""
+  "addcc %1,%1,%0")
+
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")