Backport from mainline

	2012-05-04  Uros Bizjak  <ubizjak@gmail.com>

	PR target/53228
	* config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
	(TARGET_CMOV): Rename from TARGET_CMOVE.
	(TARGET_CMOVE): New define.
	* config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
	Do not set TARGET_CMOVE here.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@187169 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c8ac83f..8ce70e3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2012-05-04  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2012-05-04  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/53228
+       * config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
+       (TARGET_CMOV): Rename from TARGET_CMOVE.
+       (TARGET_CMOVE): New define.
+       * config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
+       Do not set TARGET_CMOVE here.
+
 2012-05-04  Ulrich Weigand  <ulrich.weigand@linaro.org>
 
        Backport from mainline:

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 50ca8bf..3884c4d 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2186,7 +2186,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
 /* Feature tests against the various architecture variations, used to create
    ix86_arch_features based on the processor mask.  */
 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
-  /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro.  */
+  /* X86_ARCH_CMOV: Conditional move was added for pentiumpro.  */
   ~(m_386 | m_486 | m_PENT | m_K6),
 
   /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486.  */
@@ -3424,7 +3424,7 @@ ix86_option_override_internal (bool main_args_p)
           -mtune (rather than -march) points us to a processor that has them.
           However, the VIA C3 gives a SIGILL, so we only do that for i686 and
           higher processors.  */
-       if (TARGET_CMOVE
+       if (TARGET_CMOV
            && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
          x86_prefetch_sse = true;
        break;
@@ -3700,12 +3700,6 @@ ix86_option_override_internal (bool main_args_p)
       target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
     }
 
-  /* For sane SSE instruction set generation we need fcomi instruction.
-     It is safe to enable all CMOVE instructions.  Also, RDRAND intrinsic
-     expands to a sequence that includes conditional move. */
-  if (TARGET_SSE || TARGET_RDRND)
-    TARGET_CMOVE = 1;
-
   /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix.  */
   {
     char *p;

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 8a0e62b..a04ecf1 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -425,7 +425,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
 
 /* Feature tests against the various architecture variations.  */
 enum ix86_arch_indices {
-  X86_ARCH_CMOVE,              /* || TARGET_SSE */
+  X86_ARCH_CMOV,
   X86_ARCH_CMPXCHG,
   X86_ARCH_CMPXCHG8B,
   X86_ARCH_XADD,
@@ -436,12 +436,17 @@ enum ix86_arch_indices {
 
 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
 
-#define TARGET_CMOVE           ix86_arch_features[X86_ARCH_CMOVE]
+#define TARGET_CMOV            ix86_arch_features[X86_ARCH_CMOV]
 #define TARGET_CMPXCHG         ix86_arch_features[X86_ARCH_CMPXCHG]
 #define TARGET_CMPXCHG8B       ix86_arch_features[X86_ARCH_CMPXCHG8B]
 #define TARGET_XADD            ix86_arch_features[X86_ARCH_XADD]
 #define TARGET_BSWAP           ix86_arch_features[X86_ARCH_BSWAP]
 
+/* For sane SSE instruction set generation we need fcomi instruction.
+   It is safe to enable all CMOVE instructions.  Also, RDRAND intrinsic
+   expands to a sequence that includes conditional move. */
+#define TARGET_CMOVE           (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
+
 #define TARGET_FISTTP          (TARGET_SSE3 && TARGET_80387)
 
 extern int x86_prefetch_sse;