2006-11-07 Eric Christopher <echristo@apple.com>

        * libgcc2.c (__bswapdi2): Rename from bswapDI2.
        (__bswapsi2): Ditto.
        * libgcc2.h: Remove transformation of bswap routines.
        * config/i386/i386.md (bswapsi2): New.
        (bswapdi2): Ditto.

2006-11-07  Eric Christopher  <echristo@apple.com>

        * gcc.target/i386/builtin-bswap-1.c: Rewrite for 64-bit.
        Test using scan-assembler-not.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@118576 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 38eed0d..ec09889 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2006-11-07  Eric Christopher  <echristo@apple.com>
+
+       * libgcc2.c (__bswapdi2): Rename from bswapDI2.
+       (__bswapsi2): Ditto.
+       * libgcc2.h: Remove transformation of bswap routines.
+       * config/i386/i386.md (bswapsi2): New.
+       (bswapdi2): Ditto.
+
 2006-11-07  Jakub Jelinek  <jakub@redhat.com>
 
        * c-common.c (c_common_attributes): Add gnu_inline attribyte.
@@ -14,7 +22,7 @@
 
 2006-11-06  Anatoly Sokolov <aesok@post.ru>
 
-       * config/avr/avr-protos.h (mask_one_bit_p, const_int_pow2_p): Remove 
+       * config/avr/avr-protos.h (mask_one_bit_p, const_int_pow2_p): Remove
        prototype.
        * config/avr/avr.c (mask_one_bit_p, const_int_pow2_p): Remove.
        (output_movhi, ashlhi3_out, ashlsi3_out, ashrhi3_out, ashrsi3_out,
@@ -50,9 +58,9 @@
 
        * gcc.c (process_command): Treat -b as normal switch if its argument
        has no dash.
-       
+
 2006-11-07  David Ung  <davidu@mips.com>
-       
+
        * config/mips/mips.h (ISA_HAS_PREFETCHX): Add ISA_MIPS32R2 to the
        list.
 

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 28de0a4..b3a026a 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -278,14 +278,14 @@
     (const_int 0)))
 
 ;; Set when string REP prefix is used.
-(define_attr "prefix_rep" "" 
+(define_attr "prefix_rep" ""
   (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
     (const_int 1)
     (const_int 0)))
 
 ;; Set when 0f opcode prefix is used.
 (define_attr "prefix_0f" ""
-  (if_then_else 
+  (if_then_else
     (ior (eq_attr "type" "imovx,setcc,icmov")
         (eq_attr "unit" "sse,mmx"))
     (const_int 1)
@@ -460,7 +460,7 @@
 
 ;; All x87 floating point modes
 (define_mode_macro X87MODEF [SF DF XF])
- 
+
 ;; All integer modes handled by x87 fisttp operator.
 (define_mode_macro X87MODEI [HI SI DI])
 
@@ -469,7 +469,7 @@
 
 ;; All SSE floating point modes
 (define_mode_macro SSEMODEF [SF DF])
- 
+
 ;; All integer modes handled by SSE cvtts?2si* operators.
 (define_mode_macro SSEMODEI24 [SI DI])
 
@@ -1085,7 +1085,7 @@
 ;; Push/pop instructions.  They are separate since autoinc/dec is not a
 ;; general_operand.
 ;;
-;; %%% We don't use a post-inc memory reference because x86 is not a 
+;; %%% We don't use a post-inc memory reference because x86 is not a
 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
 ;; targets without our curiosities, and it is just as easy to represent
@@ -1147,7 +1147,7 @@
   [(set_attr "type" "alu1")
    (set_attr "mode" "SI")
    (set_attr "length_immediate" "0")])
- 
+
 (define_insn "*movsi_or"
   [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "immediate_operand" "i"))
@@ -2289,7 +2289,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], SFmode))" 
+       || memory_operand (operands[0], SFmode))"
 {
   switch (which_alternative)
     {
@@ -2349,7 +2349,7 @@
                   (const_string "V4SF"))
               /* For architectures resolving dependencies on
                  whole SSE registers use APS move to break dependency
-                 chains, otherwise use short move to avoid extra work. 
+                 chains, otherwise use short move to avoid extra work.
 
                  Do the same for architectures resolving dependencies on
                  the parts.  While in DF mode it is better to always handle
@@ -2457,7 +2457,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], DFmode))" 
+       || memory_operand (operands[0], DFmode))"
 {
   switch (which_alternative)
     {
@@ -2577,7 +2577,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], DFmode))" 
+       || memory_operand (operands[0], DFmode))"
 {
   switch (which_alternative)
     {
@@ -2693,10 +2693,10 @@
        (match_operand:DF 1 "general_operand" ""))]
   "reload_completed
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && ! (ANY_FP_REG_P (operands[0]) || 
+   && ! (ANY_FP_REG_P (operands[0]) ||
         (GET_CODE (operands[0]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
-   && ! (ANY_FP_REG_P (operands[1]) || 
+   && ! (ANY_FP_REG_P (operands[1]) ||
         (GET_CODE (operands[1]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
   [(const_int 0)]
@@ -2789,7 +2789,7 @@
    && (reload_in_progress || reload_completed
        || standard_80387_constant_p (operands[1])
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], XFmode))" 
+       || memory_operand (operands[0], XFmode))"
 {
   switch (which_alternative)
     {
@@ -2824,7 +2824,7 @@
    && (reload_in_progress || reload_completed
        || standard_80387_constant_p (operands[1])
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], XFmode))" 
+       || memory_operand (operands[0], XFmode))"
 {
   switch (which_alternative)
     {
@@ -2858,10 +2858,10 @@
   "reload_completed
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && GET_MODE (operands[0]) == XFmode
-   && ! (ANY_FP_REG_P (operands[0]) || 
+   && ! (ANY_FP_REG_P (operands[0]) ||
         (GET_CODE (operands[0]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
-   && ! (ANY_FP_REG_P (operands[1]) || 
+   && ! (ANY_FP_REG_P (operands[1]) ||
         (GET_CODE (operands[1]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
   [(const_int 0)]
@@ -3076,7 +3076,7 @@
   [(set (match_operand:HI 0 "register_operand" "")
        (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
-  "reload_completed 
+  "reload_completed
    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
    && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3146,7 +3146,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
        (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
-  "reload_completed 
+  "reload_completed
    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
    && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
   [(set (match_dup 0)
@@ -3223,7 +3223,7 @@
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3232,7 +3232,7 @@
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
        (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3311,7 +3311,7 @@
     (set_attr "mode" "DI")])
 
 ;; Extend to memory case when source register does die.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3326,7 +3326,7 @@
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
 ;; Extend to memory case when source register does not die.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3356,7 +3356,7 @@
 
 ;; Extend to register case.  Optimize case where source and destination
 ;; registers match and cases where we can use cltd.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3485,7 +3485,7 @@
 ;; These are all no-ops in the model used for the 80387.  So just
 ;; emit moves.
 
-;; %%% Kill these when call knows how to work out a DFmode push earlier. 
+;; %%% Kill these when call knows how to work out a DFmode push earlier.
 (define_insn "*dummy_extendsfdf2"
   [(set (match_operand:DF 0 "push_operand" "=<")
        (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
@@ -4371,7 +4371,7 @@
    (set_attr "i387_cw" "trunc")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (fix:DI (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4386,7 +4386,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (fix:DI (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4427,7 +4427,7 @@
    (set_attr "i387_cw" "trunc")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
        (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4440,7 +4440,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
        (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4910,7 +4910,7 @@
 
 (define_insn "*addsi3_carry_zext"
   [(set (match_operand:DI 0 "register_operand" "=r")
-         (zero_extend:DI 
+         (zero_extend:DI
            (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
                              (match_operand:SI 1 "nonimmediate_operand" "%0"))
                     (match_operand:SI 2 "general_operand" "rim"))))
@@ -5219,7 +5219,7 @@
        (compare
          (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                   (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
-         (const_int 0)))                       
+         (const_int 0)))
    (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
        (plus:DI (match_dup 1) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
@@ -5366,7 +5366,7 @@
        (compare
          (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
                   (match_operand:DI 2 "x86_64_general_operand" "rme"))
-         (const_int 0)))                       
+         (const_int 0)))
    (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT
    && ix86_match_ccmode (insn, CCGOCmode)
@@ -5565,7 +5565,7 @@
        (compare
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                   (match_operand:SI 2 "general_operand" "rmni,rni"))
-         (const_int 0)))                       
+         (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
        (plus:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
@@ -5613,7 +5613,7 @@
        (compare
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
                   (match_operand:SI 2 "general_operand" "rmni"))
-         (const_int 0)))                       
+         (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
@@ -5791,7 +5791,7 @@
        (compare
          (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
                   (match_operand:SI 2 "general_operand" "rmni"))
-         (const_int 0)))                       
+         (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
@@ -5931,7 +5931,7 @@
        (compare
          (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
                   (match_operand:HI 2 "general_operand" "rmni,rni"))
-         (const_int 0)))                       
+         (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
        (plus:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
@@ -6051,7 +6051,7 @@
        (compare
          (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
                   (match_operand:HI 2 "general_operand" "rmni"))
-         (const_int 0)))                       
+         (const_int 0)))
    (clobber (match_scratch:HI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
@@ -7421,7 +7421,7 @@
                (match_operand:DF 2 "nonimmediate_operand" "")))]
    "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
    "")
- 
+
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "register_operand" "")
        (div:SF (match_operand:SF 1 "register_operand" "")
@@ -8099,7 +8099,7 @@
            gcc_assert (INTVAL (operands[2]) == 0xffff);
            mode = HImode;
          }
-       
+
        operands[1] = gen_lowpart (mode, operands[1]);
        if (mode == QImode)
          return "movz{bq|x}\t{%1,%0|%0, %1}";
@@ -8164,7 +8164,7 @@
            gcc_assert (INTVAL (operands[2]) == 0xffff);
            mode = HImode;
          }
-       
+
        operands[1] = gen_lowpart (mode, operands[1]);
        if (mode == QImode)
          return "movz{bl|x}\t{%1,%0|%0, %1}";
@@ -8208,7 +8208,7 @@
   [(parallel [(set (zero_extract:SI (match_dup 0)
                                    (const_int 8)
                                    (const_int 8))
-                  (xor:SI 
+                  (xor:SI
                     (zero_extract:SI (match_dup 0)
                                      (const_int 8)
                                      (const_int 8))
@@ -8396,7 +8396,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (and:SI 
+       (and:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8425,7 +8425,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (and:SI 
+       (and:SI
          (zero_extract:SI
            (match_dup 1)
            (const_int 8)
@@ -8441,7 +8441,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (and:SI 
+       (and:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8459,7 +8459,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (and:SI 
+       (and:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8802,7 +8802,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (ior:SI 
+       (ior:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8819,7 +8819,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (ior:SI 
+       (ior:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8838,7 +8838,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (ior:SI 
+       (ior:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -8857,7 +8857,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (ior:SI 
+       (ior:SI
          (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
                           (const_int 8)
                           (const_int 8))
@@ -9140,7 +9140,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -9157,7 +9157,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -9176,7 +9176,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI
            (match_operand 1 "ext_register_operand" "0")
            (const_int 8)
@@ -9195,7 +9195,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
                           (const_int 8)
                           (const_int 8))
@@ -9263,7 +9263,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
          (match_dup 2)))]
   "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
@@ -9284,7 +9284,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
                         (const_int 8)
                         (const_int 8))
-       (xor:SI 
+       (xor:SI
          (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
          (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
@@ -9306,7 +9306,7 @@
      (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
                           (const_int 8)
                           (const_int 8))
-         (xor:SI 
+         (xor:SI
            (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
            (match_dup 2)))])]
   ""
@@ -9805,7 +9805,7 @@
   enum machine_mode mode = GET_MODE (operands[0]);
   enum machine_mode vmode = GET_MODE (operands[2]);
   rtx tmp;
-  
+
   operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
   operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
   if (operands_match_p (operands[0], operands[2]))
@@ -9829,7 +9829,7 @@
   "reload_completed"
   [(parallel [(set (match_dup 0) (match_dup 1))
              (clobber (reg:CC FLAGS_REG))])]
-{ 
+{
   rtx tmp;
   operands[0] = gen_lowpart (SImode, operands[0]);
   if (GET_CODE (operands[1]) == ABS)
@@ -9936,7 +9936,7 @@
   operands[1] = tmp;
 })
 
-;; Conditionalize these after reload. If they match before reload, we 
+;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
 
 (define_insn "*negsf2_1"
@@ -11350,8 +11350,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11383,8 +11383,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
   "sar{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11563,8 +11563,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11619,8 +11619,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "sar{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11720,8 +11720,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11753,8 +11753,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
   "sar{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11823,8 +11823,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11838,8 +11838,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11884,8 +11884,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -11977,7 +11977,7 @@
   "#"
   [(set_attr "type" "multi")])
 
-(define_split 
+(define_split
   [(set (match_operand:TI 0 "register_operand" "")
        (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
                     (match_operand:QI 2 "register_operand" "")))
@@ -11987,7 +11987,7 @@
   [(const_int 0)]
   "ix86_split_lshr (operands, operands[3], TImode); DONE;")
 
-(define_split 
+(define_split
   [(set (match_operand:TI 0 "register_operand" "")
        (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
                     (match_operand:QI 2 "immediate_operand" "")))
@@ -12012,8 +12012,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12045,8 +12045,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12121,7 +12121,7 @@
   [(const_int 0)]
   "ix86_split_lshr (operands, operands[3], DImode); DONE;")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
                     (match_operand:QI 2 "nonmemory_operand" "")))
@@ -12148,8 +12148,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12205,8 +12205,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12306,8 +12306,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12339,8 +12339,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12409,8 +12409,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12423,8 +12423,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12469,8 +12469,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12543,7 +12543,7 @@
 })
 
 ;; Implement rotation using two double-precision shift instructions
-;; and a scratch register.   
+;; and a scratch register.
 (define_insn_and_split "ix86_rotldi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (rotate:DI (match_operand:DI 1 "register_operand" "0")
@@ -12551,7 +12551,7 @@
   (clobber (reg:CC FLAGS_REG))
   (clobber (match_scratch:SI 3 "=&r"))]
  "!TARGET_64BIT"
- "" 
+ ""
  "&& reload_completed"
  [(set (match_dup 3) (match_dup 4))
   (parallel
@@ -12567,7 +12567,7 @@
                               (minus:QI (const_int 32) (match_dup 2)))))
     (clobber (reg:CC FLAGS_REG))])]
  "split_di (operands, 1, operands + 4, operands + 5);")
- 
+
 (define_insn "*rotlsi3_1_one_bit_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
        (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
@@ -12577,8 +12577,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{q}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12611,8 +12611,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{l}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12670,8 +12670,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{w}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12704,8 +12704,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{b}\t%0"
   [(set_attr "type" "rotate1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12718,8 +12718,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{b}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12765,9 +12765,9 @@
   emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
   DONE;
 })
-  
+
 ;; Implement rotation using two double-precision shift instructions
-;; and a scratch register.   
+;; and a scratch register.
 (define_insn_and_split "ix86_rotrdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (rotatert:DI (match_operand:DI 1 "register_operand" "0")
@@ -12801,8 +12801,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{q}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12835,8 +12835,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{l}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12850,8 +12850,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{l}\t%k0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12897,8 +12897,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{w}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12931,8 +12931,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{b}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -12945,8 +12945,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{b}\t%0"
   [(set_attr "type" "rotate1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
        (const_string "2")
        (const_string "*")))])
 
@@ -13313,14 +13313,14 @@
    (set_attr "mode" "QI")])
 
 ;; In general it is not safe to assume too much about CCmode registers,
-;; so simplify-rtx stops when it sees a second one.  Under certain 
+;; so simplify-rtx stops when it sees a second one.  Under certain
 ;; conditions this is safe on x86, so help combine not create
 ;;
 ;;     seta    %al
 ;;     testb   %al, %al
 ;;     sete    %al
 
-(define_split 
+(define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
        (ne:QI (match_operator 1 "ix86_comparison_operator"
                 [(reg FLAGS_REG) (const_int 0)])
@@ -13331,7 +13331,7 @@
   PUT_MODE (operands[1], QImode);
 })
 
-(define_split 
+(define_split
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
        (ne:QI (match_operator 1 "ix86_comparison_operator"
                 [(reg FLAGS_REG) (const_int 0)])
@@ -13342,7 +13342,7 @@
   PUT_MODE (operands[1], QImode);
 })
 
-(define_split 
+(define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
        (eq:QI (match_operator 1 "ix86_comparison_operator"
                 [(reg FLAGS_REG) (const_int 0)])
@@ -13362,7 +13362,7 @@
     FAIL;
 })
 
-(define_split 
+(define_split
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
        (eq:QI (match_operator 1 "ix86_comparison_operator"
                 [(reg FLAGS_REG) (const_int 0)])
@@ -13594,14 +13594,14 @@
             (const_int 6)))])
 
 ;; In general it is not safe to assume too much about CCmode registers,
-;; so simplify-rtx stops when it sees a second one.  Under certain 
+;; so simplify-rtx stops when it sees a second one.  Under certain
 ;; conditions this is safe on x86, so help combine not create
 ;;
 ;;     seta    %al
 ;;     testb   %al, %al
 ;;     je      Lfoo
 
-(define_split 
+(define_split
   [(set (pc)
        (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
                                      [(reg FLAGS_REG) (const_int 0)])
@@ -13616,8 +13616,8 @@
 {
   PUT_MODE (operands[0], VOIDmode);
 })
-  
-(define_split 
+
+(define_split
   [(set (pc)
        (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
                                      [(reg FLAGS_REG) (const_int 0)])
@@ -14092,7 +14092,7 @@
     return "call\t%P0";
 }
   [(set_attr "type" "call")])
-  
+
 (define_insn "*call_pop_1"
   [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
         (match_operand:SI 1 "" ""))
@@ -14428,7 +14428,7 @@
 })
 
 (define_insn_and_split "eh_return_si"
-  [(set (pc) 
+  [(set (pc)
         (unspec [(match_operand:SI 0 "register_operand" "c")]
                 UNSPEC_EH_RETURN))]
   "!TARGET_64BIT"
@@ -14438,7 +14438,7 @@
   "ix86_expand_epilogue (2); DONE;")
 
 (define_insn_and_split "eh_return_di"
-  [(set (pc) 
+  [(set (pc)
         (unspec [(match_operand:DI 0 "register_operand" "c")]
                 UNSPEC_EH_RETURN))]
   "TARGET_64BIT"
@@ -14465,7 +14465,7 @@
 \f
 (define_expand "ffssi2"
   [(parallel
-     [(set (match_operand:SI 0 "register_operand" "") 
+     [(set (match_operand:SI 0 "register_operand" "")
           (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
       (clobber (match_scratch:SI 2 ""))
       (clobber (reg:CC FLAGS_REG))])]
@@ -14473,7 +14473,7 @@
   "")
 
 (define_insn_and_split "*ffs_cmove"
-  [(set (match_operand:SI 0 "register_operand" "=r") 
+  [(set (match_operand:SI 0 "register_operand" "=r")
        (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&r"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14492,7 +14492,7 @@
   "")
 
 (define_insn_and_split "*ffs_no_cmove"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r") 
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
        (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&q"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14526,7 +14526,7 @@
 
 (define_expand "ffsdi2"
   [(parallel
-     [(set (match_operand:DI 0 "register_operand" "") 
+     [(set (match_operand:DI 0 "register_operand" "")
           (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
       (clobber (match_scratch:DI 2 ""))
       (clobber (reg:CC FLAGS_REG))])]
@@ -14534,7 +14534,7 @@
   "")
 
 (define_insn_and_split "*ffs_rex64"
-  [(set (match_operand:DI 0 "register_operand" "=r") 
+  [(set (match_operand:DI 0 "register_operand" "=r")
        (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:DI 2 "=&r"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14600,6 +14600,24 @@
   "bsr{l}\t{%1, %0|%0, %1}"
   [(set_attr "prefix_0f" "1")])
 
+(define_insn "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+       (bswap:SI (match_operand:SI 1 "register_operand" "0")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BSWAP"
+  "bswap\t%k0"
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "2")])
+
+(define_insn "bswapdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (bswap:DI (match_operand:DI 1 "register_operand" "0")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && TARGET_BSWAP"
+  "bswap\t%0"
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "3")])
+
 (define_expand "clzdi2"
   [(parallel
      [(set (match_operand:DI 0 "register_operand" "")
@@ -15012,12 +15030,12 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
        (if_then_else (eq_attr "alternative" "1")
-          (if_then_else (match_operand:SF 3 "mult_operator" "") 
+          (if_then_else (match_operand:SF 3 "mult_operator" "")
              (const_string "ssemul")
              (const_string "sseadd"))
-          (if_then_else (match_operand:SF 3 "mult_operator" "") 
+          (if_then_else (match_operand:SF 3 "mult_operator" "")
              (const_string "fmul")
              (const_string "fop"))))
    (set_attr "mode" "SF")])
@@ -15031,8 +15049,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:SF 3 "mult_operator" "")
           (const_string "ssemul")
           (const_string "sseadd")))
    (set_attr "mode" "SF")])
@@ -15046,8 +15064,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-       (if_then_else (match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+       (if_then_else (match_operand:SF 3 "mult_operator" "")
           (const_string "fmul")
           (const_string "fop")))
    (set_attr "mode" "SF")])
@@ -15061,7 +15079,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(and (eq_attr "alternative" "2")
                    (match_operand:SF 3 "mult_operator" ""))
                  (const_string "ssemul")
@@ -15070,9 +15088,9 @@
                  (const_string "ssediv")
               (eq_attr "alternative" "2")
                  (const_string "sseadd")
-              (match_operand:SF 3 "mult_operator" "") 
+              (match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15086,7 +15104,7 @@
   "TARGET_SSE_MATH
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "ssemul")
               (match_operand:SF 3 "div_operator" "")
@@ -15105,10 +15123,10 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15122,10 +15140,10 @@
           (match_operand:SF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15139,10 +15157,10 @@
           (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15158,12 +15176,12 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
        (if_then_else (eq_attr "alternative" "1")
-          (if_then_else (match_operand:DF 3 "mult_operator" "") 
+          (if_then_else (match_operand:DF 3 "mult_operator" "")
              (const_string "ssemul")
              (const_string "sseadd"))
-          (if_then_else (match_operand:DF 3 "mult_operator" "") 
+          (if_then_else (match_operand:DF 3 "mult_operator" "")
              (const_string "fmul")
              (const_string "fop"))))
    (set_attr "mode" "DF")])
@@ -15177,8 +15195,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:DF 3 "mult_operator" "")
           (const_string "ssemul")
           (const_string "sseadd")))
    (set_attr "mode" "DF")])
@@ -15192,8 +15210,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-       (if_then_else (match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+       (if_then_else (match_operand:DF 3 "mult_operator" "")
           (const_string "fmul")
           (const_string "fop")))
    (set_attr "mode" "DF")])
@@ -15207,7 +15225,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(and (eq_attr "alternative" "2")
                    (match_operand:DF 3 "mult_operator" ""))
                  (const_string "ssemul")
@@ -15216,9 +15234,9 @@
                  (const_string "ssediv")
               (eq_attr "alternative" "2")
                  (const_string "sseadd")
-              (match_operand:DF 3 "mult_operator" "") 
+              (match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15233,7 +15251,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
   [(set_attr "mode" "DF")
-   (set (attr "type") 
+   (set (attr "type")
         (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "ssemul")
               (match_operand:DF 3 "div_operator" "")
@@ -15251,8 +15269,8 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
                (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
@@ -15269,10 +15287,10 @@
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
    && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15287,10 +15305,10 @@
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
    && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15305,10 +15323,10 @@
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15322,10 +15340,10 @@
            (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15340,10 +15358,10 @@
            (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15357,8 +15375,8 @@
   "TARGET_80387
    && COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:XF 3 "mult_operator" "")
            (const_string "fmul")
            (const_string "fop")))
    (set_attr "mode" "XF")])
@@ -15371,10 +15389,10 @@
   "TARGET_80387
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15387,10 +15405,10 @@
            (match_operand:XF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15404,10 +15422,10 @@
           (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15421,10 +15439,10 @@
            (match_operand:XF 2 "register_operand" "0,f")]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15438,10 +15456,10 @@
            (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15456,10 +15474,10 @@
            (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15473,7 +15491,7 @@
   "TARGET_80387 && reload_completed
    && FLOAT_MODE_P (GET_MODE (operands[0]))"
   [(const_int 0)]
-{ 
+{
   operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
   operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
   emit_insn (gen_rtx_SET (VOIDmode, operands[0],
@@ -15868,7 +15886,7 @@
    (set_attr "mode" "XF")])
 
 ;; With sincos pattern defined, sin and cos builtin function will be
-;; expanded to sincos pattern with one of its outputs left unused. 
+;; expanded to sincos pattern with one of its outputs left unused.
 ;; Cse pass  will detected, if two sincos patterns can be combined,
 ;; otherwise sincos pattern will be split back to sin or cos pattern,
 ;; depending on the unused output.
@@ -17312,7 +17330,7 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST))
@@ -17324,7 +17342,7 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST))
@@ -17372,7 +17390,7 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST))
@@ -17383,7 +17401,7 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST))
@@ -17603,7 +17621,7 @@
    (set_attr "i387_cw" "floor")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_FLOOR))
@@ -17619,7 +17637,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_FLOOR))
@@ -17661,7 +17679,7 @@
    (set_attr "i387_cw" "floor")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_FLOOR))
@@ -17676,7 +17694,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_FLOOR))
@@ -17889,7 +17907,7 @@
    (set_attr "i387_cw" "ceil")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_CEIL))
@@ -17905,7 +17923,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
        (unspec:DI [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_CEIL))
@@ -17947,7 +17965,7 @@
    (set_attr "i387_cw" "ceil")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_CEIL))
@@ -17962,7 +17980,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
        (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
         UNSPEC_FIST_CEIL))
@@ -18399,11 +18417,11 @@
 
 (define_insn "*rep_movdi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
                            (const_int 3))
                 (match_operand:DI 3 "register_operand" "0")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (ashift:DI (match_dup 5) (const_int 3))
                 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18419,11 +18437,11 @@
 
 (define_insn "*rep_movsi"
   [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
                            (const_int 2))
                 (match_operand:SI 3 "register_operand" "0")))
-   (set (match_operand:SI 1 "register_operand" "=S") 
+   (set (match_operand:SI 1 "register_operand" "=S")
         (plus:SI (ashift:SI (match_dup 5) (const_int 2))
                 (match_operand:SI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18439,11 +18457,11 @@
 
 (define_insn "*rep_movsi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
                            (const_int 2))
                 (match_operand:DI 3 "register_operand" "0")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (ashift:DI (match_dup 5) (const_int 2))
                 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18459,10 +18477,10 @@
 
 (define_insn "*rep_movqi"
   [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (match_operand:SI 3 "register_operand" "0")
                 (match_operand:SI 5 "register_operand" "2")))
-   (set (match_operand:SI 1 "register_operand" "=S") 
+   (set (match_operand:SI 1 "register_operand" "=S")
         (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
    (set (mem:BLK (match_dup 3))
        (mem:BLK (match_dup 4)))
@@ -18477,10 +18495,10 @@
 
 (define_insn "*rep_movqi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (match_operand:DI 3 "register_operand" "0")
                 (match_operand:DI 5 "register_operand" "2")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
    (set (mem:BLK (match_dup 3))
        (mem:BLK (match_dup 4)))
@@ -18667,7 +18685,7 @@
 
 (define_insn "*rep_stosdi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
                            (const_int 3))
                 (match_operand:DI 3 "register_operand" "0")))
@@ -18685,7 +18703,7 @@
 
 (define_insn "*rep_stossi"
   [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
                            (const_int 2))
                 (match_operand:SI 3 "register_operand" "0")))
@@ -18703,7 +18721,7 @@
 
 (define_insn "*rep_stossi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
                            (const_int 2))
                 (match_operand:DI 3 "register_operand" "0")))
@@ -18721,7 +18739,7 @@
 
 (define_insn "*rep_stosqi"
   [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (match_operand:SI 3 "register_operand" "0")
                 (match_operand:SI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18738,7 +18756,7 @@
 
 (define_insn "*rep_stosqi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (match_operand:DI 3 "register_operand" "0")
                 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -19114,7 +19132,7 @@
 
 (define_insn "*movdicc_c_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
-       (if_then_else:DI (match_operator 1 "ix86_comparison_operator" 
+       (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:DI 2 "nonimmediate_operand" "rm,0")
                      (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
@@ -19157,7 +19175,7 @@
 
 (define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-       (if_then_else:SI (match_operator 1 "ix86_comparison_operator" 
+       (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:SI 2 "nonimmediate_operand" "rm,0")
                      (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
@@ -19179,7 +19197,7 @@
 
 (define_insn "*movhicc_noc"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
-       (if_then_else:HI (match_operator 1 "ix86_comparison_operator" 
+       (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:HI 2 "nonimmediate_operand" "rm,0")
                      (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
@@ -19201,7 +19219,7 @@
 
 (define_insn_and_split "*movqicc_noc"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
-       (if_then_else:QI (match_operator 1 "ix86_comparison_operator" 
+       (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
                                [(match_operand 4 "flags_reg_operand" "")
                                 (const_int 0)])
                      (match_operand:QI 2 "register_operand" "r,0")
@@ -19229,7 +19247,7 @@
 
 (define_insn "*movsfcc_1_387"
   [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
-       (if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 
+       (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
                      (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19253,7 +19271,7 @@
 
 (define_insn "*movdfcc_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
-       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
                      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19269,7 +19287,7 @@
 
 (define_insn "*movdfcc_1_rex64"
   [(set (match_operand:DF 0 "register_operand" "=f,f,r,r")
-       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
                      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19285,7 +19303,7 @@
 
 (define_split
   [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
-       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+       (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
                                [(match_operand 4 "flags_reg_operand" "")
                                 (const_int 0)])
                      (match_operand:DF 2 "nonimmediate_operand" "")
@@ -19313,7 +19331,7 @@
 
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-       (if_then_else:XF (match_operator 1 "fcmov_comparison_operator" 
+       (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand:XF 2 "register_operand" "f,0")
                      (match_operand:XF 3 "register_operand" "0,f")))]
@@ -19475,7 +19493,7 @@
 
 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
 ;; Otherwise there will be nothing to keep
-;; 
+;;
 ;; [(set (reg ebp) (reg esp))]
 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
 ;;  (clobber (eflags)]
@@ -19667,7 +19685,7 @@
       && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
     emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
                           operands[1]));
-  else 
+  else
 #endif
     emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
                                                            operands[1])));
@@ -19707,12 +19725,12 @@
            (match_operand 2 "aligned_operand" "")]))
    (clobber (reg:CC FLAGS_REG))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
-   && ((GET_MODE (operands[0]) == HImode 
+   && ((GET_MODE (operands[0]) == HImode
        && ((!optimize_size && !TARGET_FAST_PREFIX)
             /* ??? next two lines just !satisfies_constraint_K (...) */
            || GET_CODE (operands[2]) != CONST_INT
            || satisfies_constraint_K (operands[2])))
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
           && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(parallel [(set (match_dup 0)
                   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
@@ -19785,7 +19803,7 @@
    (clobber (reg:CC FLAGS_REG))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
           && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(parallel [(set (match_dup 0)
                   (neg:SI (match_dup 1)))
@@ -19798,29 +19816,29 @@
        (not (match_operand 1 "register_operand" "")))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
           && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(set (match_dup 0)
        (not:SI (match_dup 1)))]
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[1] = gen_lowpart (SImode, operands[1]);")
 
-(define_split 
+(define_split
   [(set (match_operand 0 "register_operand" "")
-       (if_then_else (match_operator 1 "comparison_operator" 
+       (if_then_else (match_operator 1 "comparison_operator"
                                [(reg FLAGS_REG) (const_int 0)])
                      (match_operand 2 "register_operand" "")
                      (match_operand 3 "register_operand" "")))]
   "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
           && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(set (match_dup 0)
        (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[2] = gen_lowpart (SImode, operands[2]);
    operands[3] = gen_lowpart (SImode, operands[3]);")
-                       
+
 \f
 ;; RTL Peephole optimizations, run before sched2.  These primarily look to
 ;; transform a complex memory operation into two memory to register operations.
@@ -19965,7 +19983,7 @@
    (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
   "")
 
-;; NOT is not pairable on Pentium, while XOR is, but one byte longer. 
+;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
 ;; Don't split NOTs with a displacement operand, because resulting XOR
 ;; will not be pairable anyway.
 ;;
@@ -19981,7 +19999,7 @@
        (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], SImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
@@ -19995,7 +20013,7 @@
        (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], HImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
@@ -20009,7 +20027,7 @@
        (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], QImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
@@ -20090,7 +20108,7 @@
              (set (zero_extract:SI (match_dup 2)
                                    (const_int 8)
                                    (const_int 8))
-                  (and:SI 
+                  (and:SI
                     (zero_extract:SI
                       (match_dup 2)
                       (const_int 8)
@@ -20192,7 +20210,7 @@
   [(set (match_operand 0 "register_operand" "")
        (const_int -1))]
   "(GET_MODE (operands[0]) == HImode
-    || GET_MODE (operands[0]) == SImode 
+    || GET_MODE (operands[0]) == SImode
     || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
    && (optimize_size || TARGET_PENTIUM)
    && peep2_regno_dead_p (0, FLAGS_REG)"
@@ -20548,7 +20566,7 @@
           (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
                    (match_operand:SI 2 "const_int_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
-  "!optimize_size 
+  "!optimize_size
    && (INTVAL (operands[2]) == 3
        || INTVAL (operands[2]) == 5
        || INTVAL (operands[2]) == 9)"
@@ -20580,7 +20598,7 @@
                    (match_operand:DI 2 "const_int_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_64BIT
-   && !optimize_size 
+   && !optimize_size
    && (INTVAL (operands[2]) == 3
        || INTVAL (operands[2]) == 5
        || INTVAL (operands[2]) == 9)"
@@ -20711,7 +20729,7 @@
    && ((!TARGET_PARTIAL_REG_STALL
        && (GET_MODE (operands[0]) == QImode
            || GET_MODE (operands[0]) == HImode))
-       || GET_MODE (operands[0]) == SImode 
+       || GET_MODE (operands[0]) == SImode
        || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
    /* We reorder load and the shift.  */
    && !rtx_equal_p (operands[1], operands[3])
@@ -20860,7 +20878,7 @@
   [(set_attr "type" "callv")])
 \f
 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
-;; That, however, is usually mapped by the OS to SIGSEGV, which is often 
+;; That, however, is usually mapped by the OS to SIGSEGV, which is often
 ;; caught for use by garbage collectors and the like.  Using an insn that
 ;; maps to SIGILL makes it more likely the program will rightfully die.
 ;; Keeping with tradition, "6" is in honor of #UD.
@@ -20968,7 +20986,7 @@
   int locality = INTVAL (operands[1]);
   gcc_assert (locality >= 0 && locality <= 3);
 
-  return patterns[locality];  
+  return patterns[locality];
 }
   [(set_attr "type" "sse")
    (set_attr "memory" "none")])
@@ -20986,7 +21004,7 @@
   int locality = INTVAL (operands[1]);
   gcc_assert (locality >= 0 && locality <= 3);
 
-  return patterns[locality];  
+  return patterns[locality];
 }
   [(set_attr "type" "sse")
    (set_attr "memory" "none")])

diff --git a/gcc/libgcc2.c b/gcc/libgcc2.c
index f3a0a24..bc50ab6 100644 (file)
--- a/gcc/libgcc2.c
+++ b/gcc/libgcc2.c
@@ -494,7 +494,7 @@ __ashrdi3 (DWtype u, word_type b)
 \f
 #ifdef L_bswapsi2
 UWtype
-__bswapSI2 (UWtype u)
+__bswapsi2 (UWtype u)
 {
   return ((((u) & 0xff000000) >> 24)
          | (((u) & 0x00ff0000) >>  8)
@@ -504,7 +504,7 @@ __bswapSI2 (UWtype u)
 #endif
 #ifdef L_bswapdi2
 UDWtype
-__bswapDI2 (UDWtype u)
+__bswapdi2 (UDWtype u)
 {
   return ((((u) & 0xff00000000000000ull) >> 56)
          | (((u) & 0x00ff000000000000ull) >> 40)
@@ -1886,7 +1886,7 @@ CONCAT3(__div,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
 {
   MTYPE denom, ratio, x, y;
 
-  /* ??? We can get better behavior from logarithmic scaling instead of 
+  /* ??? We can get better behavior from logarithmic scaling instead of
      the division.  But that would mean starting to link libgcc against
      libm.  We could implement something akin to ldexp/frexp as gcc builtins
      fairly easily...  */

diff --git a/gcc/libgcc2.h b/gcc/libgcc2.h
index 1182ba3..d15ab8d 100644 (file)
--- a/gcc/libgcc2.h
+++ b/gcc/libgcc2.h
@@ -304,13 +304,11 @@ typedef int word_type __attribute__ ((mode (__word__)));
 #define __ctzSI2       __NW(ctz,2)
 #define __popcountSI2  __NW(popcount,2)
 #define __paritySI2    __NW(parity,2)
-#define __bswapSI2     __NW(bswap,2)
 #define __ffsDI2       __NDW(ffs,2)
 #define __clzDI2       __NDW(clz,2)
 #define __ctzDI2       __NDW(ctz,2)
 #define __popcountDI2  __NDW(popcount,2)
 #define __parityDI2    __NDW(parity,2)
-#define __bswapDI2     __NDW(bswap,2)
 
 extern DWtype __muldi3 (DWtype, DWtype);
 extern DWtype __divdi3 (DWtype, DWtype);
@@ -347,13 +345,13 @@ extern Wtype __addvSI3 (Wtype, Wtype);
 extern Wtype __subvSI3 (Wtype, Wtype);
 extern Wtype __mulvSI3 (Wtype, Wtype);
 extern Wtype __negvSI2 (Wtype);
-extern UWtype __bswapSI2 (UWtype);
+extern UWtype __bswapsi2 (UWtype);
 extern DWtype __absvDI2 (DWtype);
 extern DWtype __addvDI3 (DWtype, DWtype);
 extern DWtype __subvDI3 (DWtype, DWtype);
 extern DWtype __mulvDI3 (DWtype, DWtype);
 extern DWtype __negvDI2 (DWtype);
-extern UDWtype __bswapDI2 (UDWtype);
+extern UDWtype __bswapdi2 (UDWtype);
 
 #ifdef COMPAT_SIMODE_TRAPPING_ARITHMETIC
 extern SItype __absvsi2 (SItype);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 29dfb3f..4459c08 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2006-11-07  Eric Christopher  <echristo@apple.com>
+
+       * gcc.target/i386/builtin-bswap-1.c: Rewrite for 64-bit.
+       Test using scan-assembler-not.
+
 2006-11-07  Jakub Jelinek  <jakub@redhat.com>
 
        * gcc.dg/inline-17.c: New test.
@@ -216,7 +221,7 @@
 
        PR fortran/29641
        * gfortran.dg/used_types_11.f90: New test.
-       
+
 2006-10-30  Dirk Mueller  <dmueller@suse.de>
 
        * g++.old-deja/g++.pt/eichin01a.C (main): Fix prototype.
@@ -305,7 +310,7 @@
 2006-10-28  Tobias Burnus  <burnus@net-b.de>
 
        PR libgfortran/24313
-       * gfortran.dg/csqrt_2.f: Remove xfail *-*-linux-gnu. 
+       * gfortran.dg/csqrt_2.f: Remove xfail *-*-linux-gnu.
 
 2006-10-29  Kazu Hirata  <kazu@codesourcery.com>
 
@@ -332,9 +337,9 @@
 
 2006-10-28  Tobias Burnus  <burnus@net-b.de>
 
-       PR fortran/28224 
+       PR fortran/28224
        * gfortran.dg/io_constraints_2.f90: Use -std=f95.
-       * gfortran.dg/namelist_internal.f90: New test. 
+       * gfortran.dg/namelist_internal.f90: New test.
 
 2006-10-28  Tobias Burnus  <burnus@net-b.de>
 
@@ -358,7 +363,7 @@
        * gcc.dg/builtins-44.c: Likewise.
        * gcc.dg/builtins-45.c: Likewise.
        * gcc.dg/pr28796-2.c: Likewise.
-       * gcc.dg/unordered-3.c: Likewise.       
+       * gcc.dg/unordered-3.c: Likewise.
 
 2006-10-27  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
 
@@ -416,7 +421,7 @@
 
        * gcc.dg/torture/builtin-math-2.c: Add checks for asin, acos,
        acosh and atanh.
-       
+
        * gcc.dg/torture/builtin-math-3.c (TESTIT): Append 'F' and 'L'
        floating point modifiers to arguments passed to float and long
        double functions respectively.  Update all callers to use floating
@@ -517,11 +522,11 @@
        * gcc.dg/torture/pr26898-2.c: Likewise.
 
 2006-10-20  Lee Millward  <lee.millward@codesourcery.com>
-        
+
         PR c++/28053
         * g++.dg/parse/bitfield1.C: Adjust error markers.
-        * g++.dg/parse/bitfield2.C: New test. 
-       
+        * g++.dg/parse/bitfield2.C: New test.
+
 2006-10-20  Adam Nemet  <anemet@caviumnetworks.com>
 
        * gcc.dg/tree-ssa/ivopts-2.c: Match final candidates line only.
@@ -563,7 +568,7 @@
 
        PR c++/27952
        * g++.dg/inherit/virtual1.C: New test.
-       
+
 2006-10-17  Mark Mitchell  <mark@codesourcery.com>
 
        PR c++/28261
@@ -573,7 +578,7 @@
 
        PR c++/29039
        * g++.dg/init/ctor8.C: New test.
-       
+
 2006-10-17  Mark Mitchell  <mark@codesourcery.com>
 
        PR c++/27270

diff --git a/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c b/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
index a3cf0a0..9926e18 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
+++ b/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
@@ -1,12 +1,16 @@
 /* { dg-do compile } */
-/* { dg-options "-march=i486" } */
-/* { dg-final { scan-assembler "bswap" } } */
+/* { dg-options "-march=nocona" } */
+/* { dg-final { scan-assembler-not "builtin_bswap" } } */
 
-int foo (int a)
+long foo (long a)
 {
-  int b;
+  long b;
 
-  b = __builtin_bswap (a);
+#if __LP64__
+  b = __builtin_bswap64 (a);
+#else
+  b = __builtin_bswap32 (a);
+#endif
 
   return b;
 }