PR rtl-optimization/45912

	* ira-costs.c (ira_tune_allocno_costs_and_cover_classes): Test the
	regno of registers instead of their index to compute the alignment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@165437 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb6aa57..3ad8dfd 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2010-10-13  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR rtl-optimization/45912
+       * ira-costs.c (ira_tune_allocno_costs_and_cover_classes): Test the
+       regno of registers instead of their index to compute the alignment.
+
 2010-10-13  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/i386/i386.c (ix86_build_const_vector): Check vector

diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index 3d8298d..db9ed7c 100644 (file)
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1789,15 +1789,14 @@ ira_tune_allocno_costs_and_cover_classes (void)
       if (min_cost != INT_MAX)
        ALLOCNO_COVER_CLASS_COST (a) = min_cost;
 
-      /* Some targets allow pseudos to be allocated to unaligned
-         sequences of hard registers.  However, selecting an unaligned
-         sequence can unnecessarily restrict later allocations.  So
-         increase the cost of unaligned hard regs to encourage the use
-         of aligned hard regs.  */
+      /* Some targets allow pseudos to be allocated to unaligned sequences
+        of hard registers.  However, selecting an unaligned sequence can
+        unnecessarily restrict later allocations.  So increase the cost of
+        unaligned hard regs to encourage the use of aligned hard regs.  */
       {
-       int nregs, index;
+       const int nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)];
 
-       if ((nregs = ira_reg_class_nregs[cover_class][ALLOCNO_MODE (a)]) > 1)
+       if (nregs > 1)
          {
            ira_allocate_and_set_costs
              (&ALLOCNO_HARD_REG_COSTS (a), cover_class,
@@ -1805,10 +1804,10 @@ ira_tune_allocno_costs_and_cover_classes (void)
            reg_costs = ALLOCNO_HARD_REG_COSTS (a);
            for (j = n - 1; j >= 0; j--)
              {
-               if (j % nregs != 0)
+               regno = ira_non_ordered_class_hard_regs[cover_class][j];
+               if ((regno % nregs) != 0)
                  {
-                   regno = ira_non_ordered_class_hard_regs[cover_class][j];
-                   index = ira_class_hard_reg_index[cover_class][regno];
+                   int index = ira_class_hard_reg_index[cover_class][regno];
                    ira_assert (index != -1);
                    reg_costs[index] += ALLOCNO_FREQ (a);
                  }

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3ed9a37..5d99bd6 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2010-10-13  Eric Botcazou  <ebotcazou@adacore.com>
+
+       * gcc.c-torture/execute/20101013-1.c: New test.
+
 2010-10-13  Richard Guenther  <rguenther@suse.de>
 
        PR objc/45878

diff --git a/gcc/testsuite/gcc.c-torture/execute/20101013-1.c b/gcc/testsuite/gcc.c-torture/execute/20101013-1.c
new file mode 100644 (file)
index 0000000..7d477af
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20101013-1.c
@@ -0,0 +1,36 @@
+/* PR rtl-optimization/45912 */
+
+extern void abort (void);
+
+static void* __attribute__((noinline,noclone))
+get_addr_base_and_unit_offset (void *base, long long *i)
+{
+  *i = 0;
+  return base;
+}
+
+static void* __attribute__((noinline,noclone))
+build_int_cst (void *base, long long offset)
+{
+  if (offset != 4)
+    abort ();
+
+  return base;
+}
+
+static void* __attribute__((noinline,noclone))
+build_ref_for_offset (void *base, long long offset)
+{
+  long long base_offset;
+  base = get_addr_base_and_unit_offset (base, &base_offset);
+  return build_int_cst (base, base_offset + offset / 8);
+}
+
+int
+main (void)
+{
+  void *ret = build_ref_for_offset ((void *)0, 32);
+  if (ret != (void *)0)
+    abort ();
+  return 0;
+}